Semiconductor arrangement with one or more semiconductor columns
A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.
1. A semiconductor arrangement comprising:
a substrate region;
a first semiconductor column projecting from the substrate region, wherein:
a sidewall of the first semiconductor column has a non-tapered portion and a first tapered portion,
the first tapered portion of the sidewall abuts a top surface of the first semiconductor column at which the first semiconductor column terminates, and
an interior angle defined by the first tapered portion of the sidewall and the top surface of the first semiconductor column is less than 90 degrees;
a gate electrode surrounding at least some of the first semiconductor column; and
a second semiconductor column projecting from the substrate region, the second semiconductor column separated a first distance from the first semiconductor column, the first distance between about 10 nm to about 30 nm.
2. The semiconductor arrangement of claim 1 , wherein the second semiconductor column is separated the first distance from the first semiconductor column along a first axis.
3. The semiconductor arrangement of claim 2 , comprising a fourth semiconductor column projecting from the substrate region, the fourth semiconductor column separated the first distance from the first semiconductor column along the first axis.
4. The semiconductor arrangement of claim 2 , comprising a fifth semiconductor column projecting from the substrate region, the fifth semiconductor column separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis.
5. The semiconductor arrangement of claim 1 , wherein the top surface of the first semiconductor column lies in a first plane and the non-tapered portion of the sidewall lies in a second plane perpendicular to the first plane.
6. The semiconductor arrangement of claim 1 , wherein:
the sidewall of the first semiconductor column has a second tapered portion,
the non-tapered portion is between the first tapered portion and the second tapered portion, and
the second tapered portion abuts a bottom surface of the first semiconductor column.
7. The semiconductor arrangement of claim 1 , wherein the first semiconductor column comprises at least one of silicon or polysilicon.
8. The semiconductor arrangement of claim 1 , wherein the gate electrode wraps around the non-tapered portion.
9. The semiconductor arrangement of claim 1 , wherein the top surface of the first semiconductor column extends linearly from the sidewall of the first semiconductor column to a second sidewall of the first semiconductor column.
10. A semiconductor arrangement comprising:
a substrate region;
a first semiconductor column projecting from the substrate region, wherein:
the first semiconductor column comprises:
a first end portion having a tapered sidewall abutting a top surface of the first semiconductor column at which the first semiconductor column terminates; and
a center portion having a non-tapered sidewall, and
the tapered sidewall abuts the non-tapered sidewall;
a gate electrode surrounding at least some of the first semiconductor column;
a second semiconductor column projecting from the substrate region, the second semiconductor column separated a first distance from the first semiconductor column along a first axis, the first distance between about 10 nm to about 30 nm; and
a third semiconductor column projecting from the substrate region, the third semiconductor column separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis, the second distance between about 10 nm to about 30 nm.
11. The semiconductor arrangement of claim 10 , wherein a cross-section of the first semiconductor column parallel to the top surface of the substrate region is substantially circular.
12. The semiconductor arrangement of claim 10 , comprising a fourth semiconductor column projecting from the substrate region, the fourth semiconductor column separated the first distance from the first semiconductor column along the first axis.
13. The semiconductor arrangement of claim 10 , wherein the top surface of the first semiconductor column lies in a first plane and the non-tapered sidewall lies in a second plane perpendicular to the first plane.
14. The semiconductor arrangement of claim 10 , comprising a fifth semiconductor column projecting from the substrate region, the fifth semiconductor column separated the second distance from the first semiconductor column along the second axis.
15. The semiconductor arrangement of claim 10 , wherein the top surface of the first semiconductor column extends linearly from the tapered sidewall of the first semiconductor column to a second sidewall of the first semiconductor column.
16. A semiconductor arrangement comprising:
a first semiconductor column defining a first channel of a first vertical transistor, wherein:
the first semiconductor column comprises a first end portion having a tapered sidewall abutting a top surface of a substrate region from which the first semiconductor column projects, a second end portion having a tapered sidewall abutting a top surface of the first semiconductor column, and a center portion having a non-tapered sidewall,
the first semiconductor column terminates at the top surface of the first semiconductor column,
the center portion is between the first end portion and the second end portion,
the center portion has a cross-sectional diameter parallel to the top surface of the substrate region,
the first end portion has a cross-sectional diameter, parallel to the top surface of the substrate region, that is greater than the cross-sectional diameter of the center portion, and
the second end portion has a cross-sectional diameter, parallel to the top surface of the substrate region, that is greater than the cross-sectional diameter of the center portion;
a gate electrode surrounding at least some of the first semiconductor column; and
a second semiconductor column defining a second channel of a second vertical transistor, the second semiconductor column separated a first distance from the first semiconductor column, the first distance between about 10 nm to about 30 nm.
17. The semiconductor arrangement of claim 16 , comprising a third semiconductor column defining a third channel of a third vertical transistor, the third semiconductor column separated a second distance from the first semiconductor column, the second distance between about 10 nm to about 30 nm.
18. The semiconductor arrangement of claim 17 , wherein the first distance extends along a first axis and the second distance extends along a second axis substantially perpendicular to the first axis.
19. The semiconductor arrangement of claim 16 , wherein a cross-section of the first semiconductor column parallel to the top surface of the substrate region through the center portion has a substantially quadrilateral profile.
20. The semiconductor arrangement of claim 16 , wherein a cross-section of the first semiconductor column parallel to the top surface of the substrate region through the center portion is substantially circular.