Integrated circuit with programmable storage cell array and boot-up operation method thereof
An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.
1. An integrated circuit comprising:
a first programmable storage cell group suitable for storing program validity information;
second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3; and
a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result.
2. The integrated circuit of claim 1 , wherein when the program validity information determined by the validity determination unit are invalid, the read operations for the second to N-th programmable storage cell groups are skipped.
3. The integrated circuit of claim 1 , wherein when the program validity information are valid, the read operations for the second to N-th programmable storage cell groups are sequentially performed.
4. The integrated circuit of claim 1 , wherein the number of programmable storage cells belonging to each of the first to N-th programmable storage cell groups is equal to the number of data to be read in one read operation.
5. The integrated circuit of claim 1 , wherein the first to N-th programmable storage cell groups are included in any one of an E-fuse array circuit, a NAND flash memory, a NOR flash memory, a magnetic random access memory, a spin transfer torque magnetic random access memory, a resistive random access memory, and a phase change random access memory.
6. The integrated circuit of claim further comprising:
a row control unit suitable for selecting a programmable storage cell group to be read;
a column control unit suitable for outputting the program validity information or the data from the selected programmable storage cell group;
a control unit suitable for controlling the validity determination unit, the row control unit, and the column control unit in response to a skip signal, wherein the skip signal denotes whether the read operations for the second to N-th programmable storage cell groups are to be performed or skipped and generated by the validity determination unit based on the determination result.
7. An integrated circuit comprising:
a programmable storage cell array having a plurality of cell blocks, wherein each of the cell blocks includes a specified cell page suitable for being programmed with program validity information of the corresponding cell block, and normal cell pages suitable for being programmed with normal information; and
a validity determination unit suitable for reading the program validity information of the corresponding cell block and determining whether to skip read operations for the normal cell pages of the corresponding cell block based on the read program validity information.
8. The integrated circuit of claim 7 , wherein the programmable storage cell array includes an E-fuse array.
9. The integrated circuit of claim 7 , wherein the validity determination unit activates a skip signal for controlling the read operations for the normal cell pages of the corresponding cell block to be skipped, when the read program validity information is invalid.