Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region

1. A semiconductor device, comprising:

a semiconductor layer;

a plurality of gate trenches formed in the semiconductor layer;

a gate electrode filled in the plurality of gate trenches;

a gate insulating film provided between the gate electrode and the semiconductor layer;

an n+-type emitter region, a p-type base region, and an n − -type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer;

a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n − -type drift region;

a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, an emitter trench, which is closest to one gate trench of the plurality of gate trenches, facing the one gate trench across the n − -type drift region throughout from the front surface side of the semiconductor layer to a deepest portion of the emitter trench;

a buried electrode filled in the plurality of emitter trenches with an insulating film between the buried electrode and the semiconductor layer, electrically connected with the n+-type emitter region; and

a p-type floating region formed between the plurality of emitter trenches, wherein

the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of the emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench.

2. The semiconductor device according to claim 1 , wherein the p-type floating region has a bottom portion that bulges to a back surface side of the semiconductor layer with respect to a bottom portion of the emitter trench.

3. The semiconductor device according to claim 1 , wherein the emitter trench is formed at the same depth as that of the gate trench.

4. The semiconductor device according to claim 1 , wherein the gate trenches are disposed one pair each in a transverse direction along the front surface of the semiconductor layer, and the pair of gate trenches are opposed in the transverse direction across the p-type base region that is common thereto.

5. The semiconductor device according to claim 4 , wherein one of the pair of gate trenches is disposed at an interval of 2 μm to 7 μm with respect to the other.

6. The semiconductor device according to claim 1 , wherein the n+-type emitter region has an n-type dopant concentration of 1×10 19 cm −3 to 5×10 20 cm −3 .

7. The semiconductor device according to claim 1 , wherein the p-type base region has a p-type dopant concentration of 1×10 16 cm −3 to 1×10 18 cm −3 .

8. The semiconductor device according to claim 1 , wherein the n − -type drift region has an n-type dopant concentration of 1×10 13 cm −3 to 5×10 14 cm −3 .

9. The semiconductor device according to claim 1 , wherein the p+-type collector region has a p-type dopant concentration of 1×10 15 cm −3 to 2×10 19 cm −3 .

10. The semiconductor device according to claim 1 , wherein the n+-type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.

11. The semiconductor device according to claim 1 , comprising:

a dummy trench formed spaced at a predetermined interval lateral to the gate trench so that the n+-type emitter region, the p-type base region, and the n − -type drift region are formed between the dummy trench and the gate trench;

a buried insulating film being a buried insulating film filled in the dummy trench and having an upper surface on a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, for selectively exposing as a contact region a part of the p-type base region at a part from the front surface to the upper surface in a side surface of the dummy trench; and

a contact electrode filled in a region over the buried insulating film of the dummy trench, connected to the contact region on the side surface of the dummy trench.

12. The semiconductor device according to claim 11 , wherein the semiconductor device further comprises a first buried electrode filled via an insulating film in a region under the buried insulating film of the dummy trench.

13. The semiconductor device according to claim 12 , wherein the semiconductor device has a trench unit including a pair of the dummy trenches and a gate trench sandwiched between the pair of dummy trenches.

14. The semiconductor device according to claim 12 , wherein the dummy trench serves also as the emitter trench as a result of the first buried electrode being electrically connected with the n+-type emitter region.

15. The semiconductor device according to claim 12 , wherein the semiconductor device has a trench unit including a pair of the gate trenches and a dummy trench sandwiched between the pair of gate trenches.

16. The semiconductor device according to claim 15 , wherein the first buried electrode is electrically connected with the gate electrode.

17. The semiconductor device according to claim 11 , wherein the buried insulating film has a thickness of 0.5 μm or more.