IP Library Granted Patent US 8,952,299
Granted Patent B2
US 8,952,299 · App. 13/970,207 · Granted Feb 10, 2015

Dual resistance heater for phase change devices and manufacturing method thereof

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Quick Facts
Patent No.
US 8,952,299
App. No.
13/970,207
Granted
Feb 10, 2015
Kind
B2
Abstract

A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

Claims (41)

1. A method of fabricating a phase change device, the method comprising:

forming a resistive material heater layer in a dielectric layer; the resistive material heater layer having two regions, a top surface region and a bulk region;

increasing a resistance of the top surface region of the resistive material heater layer to be a higher resistance than the bulk region;

forming a phase change material layer overlying the resistive material heater layer and the dielectric layer, the phase change material layer being in contact with the top surface region of the resistive material heater layer; and

planarizing an uppermost portion of the phase change material to be substantially coplanar with an uppermost portion of the dielectric layer.

2. The method of claim 1 , further comprising implanting ions into the top surface region to increase a resistance of the top surface region.

3. The method of claim 2 , further comprising selecting the ion implantation species to be silicon.

4. The method of claim 2 , further comprising annealing the phase change device subsequent to implanting ions to activate the implanted species.

5. The method of claim 1 , further comprising increasing a resistance of the top surface region by exposing at least the top surface region to a plasma treatment.

6. The method of claim 1 , further comprising reacting the at least the top surface region with oxygen.

7. The method of claim 1 , wherein the top surface region comprises a few surface layers.

8. A method of fabricating a memory device, the method comprising:

forming a conductive row line over a substrate;

forming a dielectric layer over the conductive row line;

forming an aperture in the dielectric layer;

forming a resistive material heater layer in the dielectric layer; the resistive material heater layer having two regions, a top surface region and a bulk region;

increasing a resistance value of the top surface region of the resistive material heater layer to be at a higher resistance value than the bulk region;

forming a phase change material layer overlying the resistive material heater layer, the phase change material layer being in contact with the top surface region of the resistive material heater layer; and

planarizing an uppermost portion of the phase change material to be substantially coplanar with an uppermost portion of the dielectric layer.

9. The method of claim 8 , further comprising:

forming at least one spacer within the aperture prior to forming the resistive material heater layer; and

forming the resistive material heater layer at least within an area located within a region circumscribed by the at least one spacer.

10. The method of claim 9 , wherein the at least one spacer comprises a dielectric material.

11. The method of claim 9 , further comprising forming the phase change material layer at least partially within an area located within a region circumscribed by the at least one spacer.

12. The method of claim 8 , wherein the phase change material comprises a material that includes at least one element from column VI of the periodic table.

13. The method of claim 8 , wherein the phase change material is a chalcogenic material.

14. The method of claim 8 , further comprising forming a silicon-implanted nitride to form an adhesion layer over the top surface region prior to forming the phase change layer.

15. The method of claim 8 , further comprising forming a conductive column line over an uppermost surface of the phase change material layer.

16. The method of claim 15 , further comprising forming a switching material layer between the uppermost surface of the phase change material layer and the conductive column line.

17. The method of claim 16 , wherein the switching material layer comprises a chalcogenide material configured not to change phase.

18. A method of fabricating a phase change memory device, the method comprising:

forming a conductive row line over a substrate;

forming a resistive material heater layer in a dielectric layer formed on the substrate; the resistive material heater layer having a top surface region and a bulk region, the bulk region being formed proximate to the conductive row line with the top surface region being formed distal from the conductive row line, and a volume of the top surface region being much smaller than a volume of the bulk region;

increasing a resistance value of the top surface region of the resistive material heater layer to be at higher resistance value than the bulk region;

forming a phase change material layer overlying the resistive material heater layer and the dielectric layer, the phase change material layer being in contact with the top surface region of the resistive material heater layer;

planarizing an uppermost portion of the phase change material to be substantially coplanar with an uppermost portion of the dielectric layer; and

forming a switching device over an uppermost surface of the phase change material layer.

19. The method of claim 18 , further comprising diffusing oxygen ions within the top surface region of the resistive material heater layer.

20. The method of claim 18 , wherein the bulk region is in electrical contact with the conductive row line.

21. The method of claim 18 , further comprising forming a conductive column line over the phase change material layer with the switching device located therebetween.

22. The method of claim 18 , wherein, prior to increasing the resistance value of the top surface region, the top surface region and the bulk region comprise the same material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →