Random telegraph signal noise reduction scheme for semiconductor memories
View Patent ↗Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.
1. A method comprising:
providing a gate signal to a selected memory cell during a single read operation, wherein the gate signal comprises a first voltage level and a second voltage level; and
sensing a data line to determine data stored on the selected memory cell;
wherein the first voltage level is substantially greater than the second voltage level, and the second voltage level is a read voltage level.
2. The method of claim 1 , wherein the first voltage level is at least approximately 1 volt greater than the read voltage level.
3. The method of claim 1 , wherein the first voltage level is greater than or equal to twice the read voltage level.
4. The method of claim 1 , wherein the selected memory cell comprises at least one of a flash memory cell, a NOR flash memory cell, a static random access memory (SRAM) cell, a phase change memory cell, and a magnetoresistive random access memory (MRAM) cell.
5. The method of claim 1 , wherein providing the gate signal to the selected memory cell comprises providing an enable signal to a transistor to enable the second voltage level to be provided to the selected memory cell.
6. The method of claim 1 , wherein the gate signal is at the second voltage level at least as long as the gate signal is at the first voltage level.
7. The method of claim 1 , wherein the second voltage level is greater than 0 volts and less than 2.0 volts.
8. A memory device comprising:
a plurality of memory cells electrically coupled together via a plurality of access lines and a plurality of data lines; and
a regulator circuit coupled to the plurality of access lines, and configured to sequentially bias at least a selected one of the plurality of access lines between a first voltage level and a second voltage level during a single read operation, wherein the first voltage level is substantially greater than the second voltage level, and the second voltage level is a read voltage level.
9. The memory device of claim 8 , wherein the regulator circuit is configured to provide a first enable signal to a first transistor to enable the first voltage level to be provided to the selected one of the plurality of access lines.
10. The memory device of claim 9 , wherein the regulator circuit is configured to provide a second enable signal to a second transistor to enable the second voltage level to be provided to the selected one of the plurality of access lines.
11. The memory device of claim 8 , wherein the regulator circuit is configured to provide an enable signal to a transistor to enable the second voltage level to be provided to the selected one of the plurality of access lines.
12. The memory device of claim 8 , wherein the second voltage level is greater than 0 volts and less than 2.0 volts, and the first voltage level is at least approximately 1 volt greater than the read voltage level.
13. The memory device of claim 8 , wherein the regulator circuit is configured to provide a third voltage level to the selected one of the plurality of access lines.
14. The memory device of claim 13 , wherein the third voltage level is approximately 0 volts.
15. A system comprising:
a memory device comprising:
a plurality of memory cells electrically coupled together via a plurality of access lines and a plurality of data lines; and
a regulator circuit coupled to the plurality of access lines, and configured to provide a first voltage level and a second voltage level to a selected one of the plurality of access lines during a single read or verify operation, wherein the first voltage level is substantially greater than the second voltage level, and the second voltage level is a read voltage level or a verify voltage level.
16. The system of claim 15 , wherein the selected one of the plurality of access lines comprises an access line coupled to a control gate of one of the plurality of memory cells.
17. The system of claim 15 , wherein the regulator circuit comprises a voltage input configured to provide the second voltage level to the selected one of the plurality of access lines.
18. The system of claim 15 , wherein the second voltage level is between 0.5 and 1.5 volts during a read operation, and the second voltage level is between 1.0 and 2.0 volts during a verify operation.
19. The system of claim 15 , wherein the regulator circuit comprises a plurality of transistors configured to enable the first voltage level and the second voltage level.
20. A method comprising:
providing a gate signal to a selected memory cell during a single read or verify operation, wherein the gate signal comprises a first voltage level and a second voltage level,
wherein the first voltage level is substantially greater than the second voltage level, and the second voltage level is a read voltage level or a verify voltage level.
21. The method of claim 20 , wherein the first voltage level is between 3.0 and 6.0 volts.
22. The method of claim 20 , wherein providing the gate signal to the selected memory cell comprises enabling a first transistor to provide the first voltage level to the selected memory cell.
23. The method of claim 22 , wherein providing the gate signal to the selected memory cell comprises enabling a second transistor to provide the second voltage level to the selected memory cell.
24. The method of claim 23 , wherein providing the gate signal to the selected memory cell comprises enabling a third transistor to provide a third voltage level to the selected memory cell.
25. The method of claim 23 , wherein providing the gate signal to the selected memory cell comprises selectively enabling a first transistor and a second transistor, wherein enabling the first transistor comprises providing the second voltage level having the read voltage level and enabling the second transistor comprises providing the second voltage level having the verify voltage level.