Distributed pin map memory
View Patent ↗In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.
1. In a testing device, a method for implementing distributed pin mapping, comprising:
receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges;
implementing accesses to the pin map memories locally at each of the plurality of bridges; and
using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.
2. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules.
3. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules and each of the pin electronics modules includes a plurality of bridge components and a plurality of CPUs.
4. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules coupled together via a high-speed bus.
5. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules having a plurality of bridge components, wherein each bridge component comprises two half bridge components, and wherein each half bridge component includes a pin map memory.
6. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules, and wherein each of the pin electronics modules is configured to couple to a plurality of devices under test.
7. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation.
8. The method of claim 1 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation including the use of a plurality of CPUs and a plurality of bridge components.
9. A non-transitory computer readable memory having computer readable code which when executed by a computer system causes the computer system to implement a method for implementing distributed pin map access, comprising:
receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges;
implementing accesses to the pin map memories locally at each of the plurality of bridges; and
using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.
10. The computer readable memory of claim 9 , wherein the testing device comprises a plurality of pin electronics modules.
11. The computer readable memory of claim 9 , wherein the testing device comprises a plurality of pin electronics modules and each of the pin electronics modules includes a plurality of bridge components and a plurality of CPUs.
12. The computer readable memory of claim 9 , wherein the testing device comprises a plurality of pin electronics modules coupled together via a high-speed bus.
13. The computer readable memory of claim 9 , wherein the testing device comprises a plurality of pin electronics modules having a plurality of bridge components, wherein each bridge component comprises two half bridge components, and wherein each half bridge component includes a pin map memory.
14. The computer readable memory of claim 9 , wherein the testing device comprises a plurality of pin electronics modules, and wherein each of the pin electronics modules is configured to couple to a plurality of devices under test.
15. The computer readable memory of claim 9 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation.
16. The computer readable memory of claim 9 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation including the use of a plurality of CPUs and a plurality of bridge components.
17. In a testing device, a method for implementing distributed pin map access, comprising:
receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges;
implementing accesses to the pin map memories locally at each of the plurality of bridges; and
using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.
18. The method of claim 17 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation.
19. The method of claim 17 , wherein the testing device comprises a plurality of pin electronics modules, and wherein the pin electronics modules can be configured to support different combined resource modes of operation including the use of a plurality of CPUs and a plurality of bridge components.