SIMPLE AND FLEXIBLE INTERFACE ARCHITECTURE FOR CONTROLLING RF FRONT-END COMPONENTS
One embodiment of the present invention provides a system for controlling at least one RF front-end component. During operation, the system receives, at a programmable logic chip from a baseband chip, a command; identifies the RF front-end component based on an address indicated by the command; and sends a control signal included in the command to the identified RF front-end component via the second interface. The programmable logic chip is coupled to the baseband chip via a first interface, and is coupled to the at least one RF front-end component via a second interface.
1 . A method for controlling one or more RF front-end components, comprising:
receiving, by a programmable logic chip from a baseband chip, a command, wherein the programmable logic chip is coupled to the baseband chip via a first interface, and wherein the programmable logic chip has a plurality of I/O pins coupled to the one or more RF front-end components;
identifying, from the plurality of I/O pins, one or more I/O pins that correspond to an RF front-end component based on an address indicated by the command; and
sending a control signal included in the command to the corresponding RF front-end component via the identified I/O pins.
2 . The method of claim 1 , wherein the first interface includes one of:
a serial peripheral interface (SPI);
an I 2 C interface;
a general purpose input/output interface; and
a serial one-wire interface.
3 . The method of claim 1 , wherein the programmable logic chip includes at least one of:
a complex programmable logic device (CPLD);
a field-programmable gate array (FPGA); and
a programmable logic device (PLA).
4 . The method of claim 1 , wherein the programmable logic chip is coupled to an RF front-end component via a second interface, wherein the second interface includes one or more of:
a serial peripheral interface (SPI);
an I 2 C interface;
a general purpose input/output interface; and
a serial one-wire interface.
5 . The method of claim 1 , wherein the command includes at least one of: a write command and a read command.
6 . The method of claim 5 , further comprising:
in response to the read command, obtaining a status reading from the corresponding RF front-end component; and
sending the status reading to the baseband chip.
7 . The method of claim 1 , wherein the RF front-end component includes one or more of:
a filter;
a band-selection switch;
a power amplifier;
a low-noise amplifier; and
an automatic gain control (AGC) circuitry.
8 . An interfacing mechanism for enabling control of one or more RF front-end components, comprising:
a programmable logic chip having a first interface for coupling to a baseband chip, and a plurality of I/O pins coupled to the one or more RF front-end components;
wherein the programmable logic chip is configured to:
receive, from the baseband chip via the first interface, a command;
identify, from the plurality of I/O pins, one or more I/O pins that correspond to an RF front-end component based on an address indicated by the command; and
send a control signal included in the command to the corresponding RF front-end component via the identified I/O pins.
9 . The interfacing mechanism of claim 8 , wherein the first interface includes one of:
a serial peripheral interface (SPI);
an I2C interface;
a general purpose input/output interface; and
a serial one-wire interface.
10 . The interfacing mechanism of claim 8 , wherein the programmable logic chip includes at least one of:
a complex programmable logic device (CPLD);
a field-programmable gate array (FPGA); and
a programmable logic device (PLA).
11 . The interfacing mechanism of claim 8 , wherein the programmable logic chip has a second interface for coupling to an RF front-end component, wherein the second interface includes one or more of:
a serial peripheral interface (SPI);
an I2C interface;
a general purpose input/output interface; and
a serial one-wire interface.
12 . The interfacing mechanism of claim 8 , wherein the command includes at least one of: a write command and a read command.
13 . The interfacing mechanism of claim 12 , wherein the programmable logic chip is further configured to:
in response to the read command, obtain a status reading from the corresponding RF front-end component; and
send the status reading to the baseband chip.
14 . The interfacing mechanism of claim 8 , wherein the RF front-end component includes one or more of:
a filter;
a band-selection switch;
a power amplifier;
a low-noise amplifier; and
an automatic gain control (AGC) circuitry.