IP Library Granted Patent US 9,129,936
Granted Patent B2
US 9,129,936 · App. 13/975,421 · Granted Sep 8, 2015

Devices, components and methods combining trench field plates with immobile electrostatic charge

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,129,936
App. No.
13/975,421
Granted
Sep 8, 2015
Kind
B2
Abstract

N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

Claims (34)

1. A semiconductor device, comprising:

a current-controlling structure, which injects first-type charge carriers into a semiconductor drift region under some but not all conditions;

a trench, abutting said drift region, which contains one or more conductive field plates, and which also contains immobile net electrostatic charge of at least 5E10 cm −2 ; and

a drain region;

wherein said field plates collectively have a vertical extent which is more than 50% of that of said trench in proximity to said drift region; and

wherein said immobile net electrostatic charge tends to invert adjacent portions of said drift region.

2. The device of claim 1 , wherein the first conductivity type is n-type.

3. The device of claim 1 , wherein said first-type charge carriers are electrons.

4. The device of claim 1 , wherein said drift region consists essentially of silicon.

5. The device of claim 1 , wherein each said trench includes only one said field plate.

6. The device of claim 1 , comprising a plurality of said trenches.

7. The device of claim 1 , wherein said field plate is heavily doped polysilicon.

8. The device of claim 1 , wherein said current-controlling structure comprises a first-conductivity-type source region, and a gate electrode which is capacitively coupled to a second-conductivity-type body region.

9. The device of claim 1 , wherein said field plate is insulated from said drift region by silicon dioxide.

10. The device of claim 1 , wherein said drift region includes paralleled p-type and n-type regions.

11. The device of claim 1 , wherein said current-controlling structure comprises a vertical field-effect-transistor channel.

12. A semiconductor device, comprising:

a current-controlling structure, which injects first-type charge carriers into a semiconductor drift region under some but not all conditions;

a trench, abutting said drift region, which contains one or more conductive field plates, and which also contains immobile net electrostatic charge of at least 5E10 cm −2 ;

wherein said charge carriers can pass through said drift region to a first-conductivity-type drain region;

wherein said field plates collectively have a volume which is more than 50% of that of said trench in proximity to said drift region; and

wherein said immobile net electrostatic charge tends to invert adjacent portions of said drift region.

13. The device of claim 12 , wherein said first-type charge carriers are electrons, and wherein said drain is n-type.

14. The device of claim 12 , wherein said drift region consists essentially of silicon.

15. The device of claim 12 , wherein each said trench includes only one said field plate.

16. The device of claim 12 , comprising a plurality of said trenches.

17. The device of claim 12 , wherein said field plate is heavily doped polysilicon.

18. The device of claim 12 , wherein said current-controlling structure comprises a first-conductivity-type source region, and a gate electrode which is capacitively coupled to a second-conductivity-type body region.

19. The device of claim 12 , wherein said field plate is insulated from said drift region by silicon dioxide.

20. A semiconductor device, comprising:

an n-type source, a p-type body region, and an insulated gate electrode which is capacitively coupled to invert portions of said body region and thereby inject electrons into a semiconductor p-type drift region;

a trench, abutting said drift region, which contains at least one conductive field plate, and which also contains immobile net electrostatic charge in a concentration sufficient to invert portions of said p-type drift region in proximity to said trench; and

an n-type drain region underlying said drift region;

wherein said field plate has sidewalls which are predominantly vertical and parallel to a sidewall of said trench.

Assignments (1)
SECURITY INTEREST Recorded Dec 27, 2022
From: MAXPOWER SEMICONDUCTOR, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062228/0648 →