IP Library › Granted Patent US 8,796,817
Granted Patent B2
US 8,796,817 · App. 13/975,505 · Granted Aug 5, 2014

Semiconductor device

Inventor: Toshio Okuda (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H01L23/5226
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Quick Facts
Patent No.
US 8,796,817
App. No.
13/975,505
Granted
Aug 5, 2014
Kind
B2
Abstract

A semiconductor device includes a multilayer substrate, a semiconductor element secured to an upper surface of the multilayer substrate, a first metal pattern located on a portion of a lower surface of the multilayer substrate, a dielectric having a higher permittivity than the multilayer substrate and located on the lower surface of the multilayer substrate, and a bottom surface electrode located on a bottom surface of the semiconductor device. The bottom surface electrode, the dielectric, and the first metal pattern together form a bypass capacitor.

Claims (14)

1. A semiconductor device comprising:

a multilayer substrate having upper and lower surfaces and a permittivity;

a semiconductor element secured to said upper surface of said multilayer substrate;

an intra-substrate via that is connected electrically to said semiconductor element and located in said multilayer substrate, extending to said lower surface of said multilayer substrate;

a first metal pattern located on a portion of said lower surface of said multilayer substrate;

a second metal pattern in contact with a lower end of said intra-substrate via;

a dielectric having a higher permittivity than the permittivity of said multilayer substrate and located on said lower surface of said multilayer substrate, covering said first and second metal patterns;

a first intra-dielectric via located in said dielectric, connected at an upper end to said first metal pattern, and extending to a lower surface of said dielectric;

a second intra-dielectric via located in said dielectric, connected at an upper end to said second metal pattern, and extending to said lower surface of said dielectric;

a ground pattern connected to a lower end of said first intra-dielectric via; and

a bottom surface electrode connected to a lower end of said second intra-dielectric via, wherein

a portion of said first metal pattern is disposed on said dielectric directly opposite a portion of said bottom surface electrode, and

said bottom surface electrode, said dielectric, and said first metal pattern, together, constitute a bypass capacitor.

2. The semiconductor device according to claim 1 , wherein said dielectric has a relative permittivity of at least 1000.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2017
From: MITSUBISHI ELECTRIC CORPORATION
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 040839/0688 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: OKUDA, TOSHIO
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 031097/0906 →
Priority Claims (1)
JP 2012-272489 · Dec 13, 2012 · national
Continuity (1)
Related Publication 20140167282A1 · Jun 19, 2014