Instruction for element offset calculation in a multi-dimensional array
An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure.
1. A processor comprising:
a decoder to decode an instruction into a decoded instruction; and
an execution unit to execute the decoded instruction to:
read a first input vector operand having an element for each dimension of a multi-dimensional structure, each element of said first input vector operand to specify a size of its respective dimension,
read a second input vector operand to specify coordinates of a particular segment of said multi-dimensional structure, and
calculate an address offset for said particular segment relative to an address of an origin segment of said multi-dimensional structure.
2. The processor of claim 1 further comprising a register to store said address of said origin segment.
3. The processor of claim 2 further comprising an adder coupled to said register, said adder to calculate an address for said particular segment.
4. The processor of claim 1 wherein said execution unit is to execute the decoded instruction to calculate:
(Y_(N−1)*X_(N−2)*X_(N−3) . . . X_(1)*X_(0))+
(Y_(N−2)*X_(N−3) . . . X_(1)*X_(0))+ . . . +
(Y_(1)*X_(0))+
(Y_(0)),
wherein N is a number of dimensions of said multi-dimensional structure, X is said first vector input operand, and Y is said second vector input operand.
5. The processor of claim 1 wherein the execution unit is to cause the address offset to be stored in a register.
6. The processor of claim 1 wherein the execution unit is to cause the address offset to be stored in scalar register space.
7. A method comprising:
decoding an instruction into a decoded instruction; and
executing the decoded instruction to:
read a first input vector operand having an element for each dimension of a multi-dimensional structure, each element of said first input vector operand specifying a size of its respective dimension,
read a second input vector operand specifying coordinates of a particular segment of said multi-dimensional structure, and
calculate an address offset for said particular segment relative to an address of an origin segment of said multi-dimensional structure.
8. The method of claim 7 further comprising fetching said address of said origin segment.
9. The method of claim 8 further comprising adding said address of said origin segment.
10. The method of claim 7 wherein said executing comprises calculating:
(Y_(N−1)*X_(N−2)*X_(N−3) . . . X_(1)*X_(0))+
(Y_(N−2)*X_(N−3) . . . X_(1)*X_(0))+ . . . +
(Y_(1)*X_(0))+
(Y_(0)),
wherein N is a number of dimensions of said multi-dimensional structure, is said first vector input operand, and Y is said second vector input operand.
11. The method of claim 7 further comprising storing the address offset in scalar register space.
12. The method of claim 7 further comprising storing the address offset in vector register space.
13. A method comprising:
decoding an instruction into a decoded instruction; and
executing the decoded instruction to:
read a first input vector operand having an element for each dimension of a multi-dimensional structure, each element of said first input vector operand specifying a size of its respective dimension,
read a second input vector operand specifying coordinates of a particular segment of said multi-dimensional structure,
calculate an address offset for said particular segment relative to an address of an origin segment of said multi-dimensional structure, and
apply said address offset to said address of said origin segment to construct an address for said particular segment; and
using said address for said particular segment to access data for said particular segment.
14. The method of claim 13 further comprising fetching said address of said origin segment.
15. The method of claim 14 further comprising storing the address offset in scalar register space.
16. The method of claim 14 further comprising storing the address offset in vector register space.
17. The method of claim 14 wherein said access includes appending lower ordered bits to said address for said particular segment.
18. The method of claim 14 wherein said address of said origin segment is not zero.
19. The method of claim 14 further comprising storing the address offset into a register from which an input operand for said executing was provided.
20. The method of claim 13 wherein said executing comprises calculating:
(Y_(N−1)*X_(N−2)*X_(N−3) . . . X_(1)*X_(0))+
(Y_(N−2)*X_(N−3) . . . X_(1)*X_(0))+ . . . +
(Y_(1)*X_(0))+
(Y_(0)),
wherein N is a number of dimensions of said multi-dimensional structure, X is said first vector input operand, and Y is said second vector input operand.