Circuit and method

1. A circuit, comprising:

a digital-to-time converter comprising a high-frequency input configured to receive a high-frequency signal, a digital input configured to receive a first digital signal, and a high-frequency output configured to provide a chronologically delayed version of the high-frequency signal; and

an oscillator arrangement configured to provide the high-frequency signal having a phase-locked loop configured to provide a frequency of the high-frequency signal; and

wherein the digital-to-time converter is configured to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.

2. The circuit according to claim 1 , wherein the oscillator arrangement is further configured to vary a phase of the high-frequency signal based on an additional digital signal.

3. The circuit according to claim 1 , further comprising:

a polar coordinate provider configured to provide a first phase signal that determines a phase modification or a phase of the delayed version of the high-frequency signal; and

wherein the first phase signal includes the first digital signal or is the first digital signal.

4. The circuit according to claim 3 :

wherein the polar coordinate provider is configured to provide the first phase signal in such a manner that it includes the first digital signal and an additional digital signal;

wherein the polar coordinate provider is further configured to provide the digital-to-time converter with the first digital signal, and to provide the additional digital signal to the oscillator arrangement; and

wherein the polar coordinate provider is further configured to provide the first digital signal and the additional digital signal in such a manner that the first digital signal determines a first fraction of the phase or the phase modification of the delayed version of the high-frequency signal, and the additional digital signal determines a second fraction of the phase or the phase modification of the delayed version of the high-frequency signal, such that the first digital signal and the additional digital signal together completely determine the phase or the phase modification of the delayed version of the high-frequency signal.

5. The circuit according to claim 4 , wherein the polar coordinate provider is further configured in such a manner that the first digital signal and the additional digital signal are provided in such a manner that the first fraction of the phase or the phase modification of the delayed version of the high-frequency signal is larger than the second fraction of the phase or the phase modification of the delayed version of the high-frequency signal.

6. The circuit according to claim 1 , further comprising a digital-to-analog converter arrangement which is configured to provide an amplitude-modulated signal based on a received digital amplitude signal.

7. The circuit according to claim 6 , further comprising an amplifier configured to amplify the delayed version of the high-frequency signal based on the amplitude-modulated signal.

8. The circuit according to claim 6 , further comprising a mixer configured to mix the amplitude-modulated signal and the delayed version of the high-frequency signal.

9. The circuit according to claim 1 , further comprising:

an additional digital-to-time converter having a high-frequency input configured to receive the high-frequency signal, a digital input configured to receive a second digital signal, and a high-frequency output configured to provide a further chronologically delayed version of the high-frequency signal; and

wherein the additional digital-to-time converter is configured to chronologically delay the received high-frequency signal based on the second digital signal received at its digital input.

10. The circuit according to claim 9 , further comprising:

a polar coordinate provider configured to provide a first phase signal that includes the first digital signal and an additional digital signal, and to provide a second phase signal that includes the second digital signal and the additional digital signal;

wherein the first phase signal determines a phase or a phase modification of the delayed version of the high-frequency signal, and the second phase signal determines a phase or a phase modification of the additional delayed version of the high-frequency signal;

wherein the first digital signal determines a first fraction of the phase or the phase modification of the delayed version of the high-frequency signal, and the additional digital signal determines a second fraction of the phase or the phase modification of the delayed version of the high-frequency signal; and

wherein the second digital signal determines a first fraction of the phase or the phase modification of the additional delayed version of the high-frequency signal, and the additional digital signal further determines a second fraction of the phase or the phase modification of the additional delayed version of the high-frequency signal, in such a manner that the second fraction of the phase or the phase modification of the additional delayed version of the high-frequency signal is the same as the second fraction of the phase or the phase modification of the delayed version of the high-frequency signal.

11. The circuit according to claim 10 :

wherein the polar coordinate provider is configured to provide the digital-to-time converter with the first digital signal, the oscillator arrangement with the additional digital signal, and the additional digital-to-time converter with the second digital signal; and

wherein the oscillator arrangement is configured to vary a phase of the high-frequency signal based on the received additional digital signal.

12. The circuit according to claim 10 , wherein the polar coordinate provider is configured to provide the first digital signal, the second digital signal, and the additional digital signal in such a manner that the first fraction of the phase or the phase modification of the delayed version of the high-frequency signal and the first fraction of the phase or the phase modification of the additional delayed version of the high-frequency signal are larger than the second fraction of the phase or the phase modification of the delayed version of the high-frequency signal and the second fraction of the phase or the phase modification of the additional delayed version of the high-frequency signal.

13. The circuit according to claim 10 , wherein the polar coordinate provider is configured to provide the first digital signal and the second digital signal in such a manner that a difference between the phase of the delayed version of the high-frequency signal and the phase of the additional delayed version of the high-frequency signal is based on a difference between the first digital signal and the second digital signal.

14. The circuit according to claim 9 , further comprising:

a polar coordinate provider configured to provide a first phase signal that determines a phase or a phase modification of the delayed version of the high-frequency signal, and to provide a second phase signal that determines a phase or a phase modification of the additional delayed version of the high-frequency signal;

wherein the first phase signal includes the first digital signal or is the first digital signal;

wherein the second phase signal includes the second digital signal or is the second digital signal;

wherein the polar coordinate provider is further configured to provide a first digital amplitude signal and a second digital amplitude signal.

15. The circuit according to claim 14 , further comprising:

a first digital-to-analog converter arrangement configured to provide a first amplitude-modulated signal based on the first digital amplitude signal; and

a second digital-to-analog converter arrangement configured to provide a second amplitude-modulated signal based on the second digital amplitude signal.

16. The circuit according to claim 15 , further comprising:

a first amplifier configured to amplify the delayed version of the high-frequency signal based on the first amplitude-modulated signal; and

a second amplifier configured to amplify the delayed version of the high-frequency signal based on the second amplitude-modulated signal.

17. The circuit according to claim 15 , further comprising:

a first mixer configured to mix the first amplitude-modulated signal with the delayed version of the high-frequency signal; and

a second mixer configured to mix the second amplitude-modulated signal with the additional delayed version of the high-frequency signal.

18. The circuit according to one claim 1 , further comprising:

a polar coordinate provider configured to provide the first digital signal in such a manner that same comprises a superposition of multiple payload data signals, of which one payload data signal can consist of a signal with a prespecified constant frequency.

19. The circuit according to claim 1 , wherein the first digital signal and the high-frequency signal are selected in such a manner that the frequency of the high-frequency signal is not a harmonic of the frequency of the delayed version of the high-frequency signal.

20. The circuit according to claim 1 :

wherein the digital-to-time converter is configured to divide down the frequency of the high-frequency signal to a divider value which is based on the first digital signal; and

wherein the circuit further comprises a polar coordinate provider which is configured to provide the first digital signal in such a manner that the divider value is not an integer number.

21. The circuit according to claim 1 , further comprising:

a polar coordinate provider configured to provide the digital-to-time converter with the first digital signal and to provide an additional digital signal to the oscillator arrangement for the purpose of adjusting the frequency of the high-frequency signal, according to a prespecified phase or phase modification of the delayed version of the high-frequency signal;

wherein the polar coordinate provider is further configured to provide the additional digital signal for the prespecified phase or phase modification of the delayed version of the high-frequency signal in a first mode, in such a manner that the high-frequency signal takes on a first frequency, and to provide the additional digital signal in a second mode, in such a manner that the high-frequency signal takes on a second frequency, wherein the first and the second frequency are different from each other and are not harmonics of each other.

22. The circuit according to claim 21 , wherein the polar coordinate provider is further configured to provide the first digital signal in the first mode and the second mode in such a manner that for the prespecified phase or phase modification of the delayed version of the high-frequency signal, a resulting frequency of the delayed version of the high-frequency signal in the first mode is the same as a resulting frequency of the delayed version of the high-frequency signal in the second mode.

23. A circuit arrangement, comprising:

a circuit, comprising:

a digital-to-time converter comprising a high-frequency input configured to receive a high-frequency signal, a digital input configured to receive a first digital signal, and a high-frequency output configured to provide a chronologically delayed version of the high-frequency signal; and

an oscillator arrangement configured to provide the high-frequency signal having a phase-locked loop configured to provide a frequency of the high-frequency signal;

wherein the digital-to-time converter is configured to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input;

a polar coordinate provider configured to provide the digital-to-time converter with the first digital signal and to provide an additional digital signal to the oscillator arrangement for the purpose of adjusting the frequency of the high-frequency signal, according to a pre-specified phase or phase modification of the delayed version of the high-frequency signal;

wherein the polar coordinate provider is further configured to provide the additional digital signal for the pre-specified phase or phase modification of the delayed version of the high-frequency signal in a first mode, in such a manner that the high-frequency signal takes on a first frequency, and to provide the additional digital signal in a second mode, in such a manner that the high-frequency signal takes on a second frequency, wherein the first and the second frequency are different from each other and are not harmonics of each other; and

a further oscillator circuit configured to generate an oscillator signal in an active state, wherein the same comprises a frequency which is a harmonic of the first frequency of the high-frequency signal,

wherein the circuit is configured to switch from the first mode into the second mode upon the activation of the further oscillator circuit.

24. A device, comprising:

a baseband processor;

an antenna port; and

a circuit which is coupled to the baseband processor and the antenna port, wherein the circuit comprises:

a digital-to-time converter comprising a high-frequency input configured to receive a high-frequency signal, a digital input configured to receive a first digital signal, and a high-frequency output configured to provide a chronologically delayed version of the high-frequency signal; and

an oscillator arrangement configured to provide the high-frequency signal having a phase-locked loop configured to provide a frequency of the high-frequency signal; and

wherein the digital-to-time converter is configured to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.

25. A method, comprising:

providing a high-frequency signal, wherein a frequency of the high-frequency signal is adjusted by means of a phase-locked loop;

receiving a first digital signal; and

chronologically delaying the high-frequency signal by means of a digital-to-time conversion based on the first digital signal, in order to obtain a delayed version of the high-frequency signal.

26. A computer program having a program code stored in a non-transitory storage medium, for executing a method when the program is executed on a computer, comprising:

providing a high-frequency signal, wherein a frequency of the high-frequency signal is adjusted by means of a phase-locked loop;

receiving a first digital signal; and

chronologically delaying the high-frequency signal by means of a digital-to-time conversion based on the first digital signal, in order to obtain a delayed version of the high-frequency signal.