Transceiver with sub-sampling based frequency synthesizer
Disclosed is a transceiver including a sub-sampling based frequency synthesizer with a sampling frequency f smp , configured to generate M different output signals 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception. M is an integer greater than 4, each output signal has a corresponding predefined frequency. The predefined frequencies are within a frequency band with a predefined bandwidth CFR. CFR is greater than f smp . The frequency synthesizer includes a frequency shift unit configured for shifting a version of the output signal over a predefined frequency shift f shift to obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer, wherein −f smp /2≦f shift ≦+f smp /2. The frequency shift unit is configured to use for the generation of each of the N different output signals a corresponding predefined frequency shift f shift .
1. A transceiver comprising
a frequency synthesizer configured to generate M different output signals for use as one or more of a carrier signal for transmission and a signal with a channel frequency for reception,
wherein M is an integer greater than 4, each output signal has a corresponding predefined frequency, and the predefined frequencies are within a frequency band with a predefined channel frequency-range (CFR),
wherein the frequency synthesizer is a sub-sampling based frequency synthesizer with a sampling frequency f smp , wherein CFR is greater than f smp , the frequency synthesizer comprising a frequency shift unit based on a Hartley modulator and configured for shifting a version of the output signal over a predefined frequency shift f shift to obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer,
wherein −f smp /2≦f shift ≦f smp /2 and the frequency shift unit is configured to use for the generation of each of the M different output signals corresponding predefined frequency shift f shift , wherein f smp is a multiple of f shift .
2. The transceiver of claim 1 , wherein the sub-sampling based frequency synthesizer is a sub-sampling based frequency locked loop frequency synthesizer.
3. The transceiver of claim 1 , wherein f smp =2 x ×f shift , wherein x is an integer greater than 0.
4. The transceiver of claim 1 , wherein the sampling unit is a binary sampler.
5. The transceiver of claim 1 , wherein the version of the output signal is in the form of single-ended or balanced quadrature phase signals.
6. The transceiver of claim 5 , wherein the frequency shift unit is configured to combine the single-ended or balanced quadrature phase signals to obtain the frequency shifted signal.
7. The transceiver of claim 6 , wherein the frequency shift unit comprises input terminals to receive the single-ended or balanced quadrature phase signals, one or two output terminals, and between any combination of the input terminal and the output terminal a switch to couple the input terminal to the output terminal, wherein the frequency shift unit further comprises a control signal generation unit configured for generating control signals to control the switches.
8. The transceiver of claim 7 , wherein the control signals generator is a type of Low Frequency Local Oscillator to generate control signals in the form of quadrature phase signals.
9. The transceiver of claim 7 , wherein the switches have switching instants which differs from switching instants of switches of the sampling unit.
10. The transceiver of claim 9 , wherein sampling instants of the sampling unit are in response to a positive edge of a sampling clock signal and the switching instants of the switches are in response to a negative edge of the sampling clock signal.
11. The transceiver of claim 9 , wherein sampling instants of the sampling unit are in response to a negative edge of a sampling clock signal and the switching instants of the switches are in response to a positive edge of the sampling clock signal.
12. The transceiver of claim 1 , further configured to operate in a multitude of channel states, wherein each channel state has a corresponding transmission and receiving frequency generated by the frequency synthesizer, wherein the predefined frequency shift f shift , the frequency of the frequency shifted output signal f mix,t when generating the transmission frequency and the frequency of the shifted output signal f mix,r when generating the receiving frequency applies to the following equation:
( f smp /2)×truncate( f mix,t /f smp /2)< f mix,r <( f smp /2)×(1+truncate( f mix,t /f smp /2)).
13. The transceiver of claim 1 , wherein the transceiver is an IEEE 802.15.4 transceiver.
14. A frequency synthesizer for use in a communication device,
wherein the frequency synthesizer is configured to generate M different output signals for use as one or more of a carrier signal for transmission and a signal with a channel frequency for reception,
wherein M is an integer greater than 4, each output signal has a corresponding predefined frequency, and the predefined frequencies are within a frequency band with a predefined channel frequency-range (CFR),
wherein the frequency synthesizer is a sub-sampling based frequency synthesizer with a sampling frequency f smp , wherein CFR is greater than f smp , the frequency synthesizer comprising a frequency shift unit based on a Hartley modulator and configured for shifting a version of the output signal over a predefined frequency shift f shift to obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer,
wherein −f smp /2≦f shift ≦+f smp /2 and the frequency shift unit is configured to use for the generation of each of the M different output signals corresponding predefined frequency shift f shift , wherein f smp is a multiple of f shift .
15. The frequency synthesizer of claim 14 , wherein the sub-sampling based frequency synthesizer is a sub-sampling based frequency locked loop frequency synthesizer.
16. The frequency synthesizer of claim 14 , wherein f smp =2 x ×f shift , wherein x is an integer greater than 0.
17. The frequency synthesizer of claim 14 , wherein the sampling unit is a binary sampler.
18. The frequency synthesizer of claim 14 , wherein the version of the output signal is in the form of single-ended or balanced quadrature phase signals.
19. The frequency synthesizer of claim 18 , wherein the frequency shift unit is configured to combine the single-ended or balanced quadrature phase signals to obtain the frequency shifted signal.
20. The frequency synthesizer of claim 19 , wherein the frequency shift unit comprises input terminals to receive the single-ended or balanced quadrature phase signals, one or two output terminals, and between any combination of the input terminal and the output terminal a switch to couple the input terminal to the output terminal, wherein the frequency shift unit further comprises a control signal generation unit configured for generating control signals to control the switches.
21. The frequency synthesizer of claim 20 , wherein the control signals generator is a type of Low Frequency Local Oscillator to generate control signals in the form of quadrature phase signals.
22. The frequency synthesizer of claim 20 , wherein the switches have switching instants which differs from switching instants of switches of the sampling unit.
23. The frequency synthesizer of claim 22 , wherein sampling instants of the sampling unit are in response to a positive edge of a sampling clock signal and the switching instants of the switches are in response to a negative edge of the sampling clock signal.
24. The frequency synthesizer of claim 22 , wherein sampling instants of the sampling unit are in response to a negative edge of a sampling clock signal and the switching instants of the switches are in response to a positive edge of the sampling clock signal.