IP Library › Granted Patent US 10,116,932
Granted Patent B2
US 10,116,932 · App. 13/992,432 · Granted Oct 30, 2018

Image filter device, decoding device, encoding device, and data structure

Inventor: Tomohiro Ikai (Osaka, JP)
Assignee: Sharp Kabushiki Kaisha
H04N19/0089H04N19/117H04N19/167H04N19/176H04N19/593H04N19/82
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Quick Facts
Patent No.
US 10,116,932
App. No.
13/992,432
Granted
Oct 30, 2018
Kind
B2
Abstract

A loop filter ( 16 ) includes a filter processing unit ( 162 c ) configured to generate an output image by acting on an input image made up of a plurality of unit regions, and a reference region setting unit ( 162 b ) configured to reduce a reference region to be referenced by the filter processing unit ( 162 c ) for calculating a pixel value of each target pixel to a size according to a position of this target pixel in a unit region including this target pixel.

Claims (15)

1. An image filter device comprising:

a deblocking filter that performs deblocking on first target pixels in side boundaries of a unit region and generates a deblocked image including the unit region;

filter circuitry that performs adaptive filtering on second target pixels in the unit region of the deblocked image, wherein the second target pixels are all pixels included in the unit region; and

reference region setting circuitry that sets a reference region to be referenced by the filter circuitry to calculate a pixel value of one of the second target pixels according to a position of the one of the second target pixels in the unit region;

wherein the reference region setting circuitry includes:

first setting circuitry that sets a position of an upstream edge of the reference region lower than or equal to a virtual boundary line, which separates the unit region into an upstream side and a downstream side, when the one of the second target pixels is on the downstream side, and

second setting circuitry that sets a position of a downstream edge of the reference region higher than the virtual boundary line, which separates the unit region into the upstream side and the downstream side, when the one of the second target pixels is on the upstream side; wherein

the deblocking filter, the filter circuitry, and the reference region setting circuitry are implemented by one or more processors.

2. The image filter device according to claim 1 , wherein

the first setting circuitry sets, when the one of the second target pixels is on the downstream side, the position of the upstream edge of the reference region to restrict a distance between the upstream edge of the reference region and the one of the second target pixels shorter than or equal to a distance between the one of the second target pixels and the virtual boundary line; and

the second setting circuitry sets, when the one of the second target pixels is on the upstream side, the position of the downstream edge of the reference region to restrict a distance between the downstream edge of the reference region and the one of the second target pixels shorter than or equal to the distance between the one of the second target pixels and the virtual boundary line.

3. A decoding device comprising:

the image filter device according to claim 1 , causing the image filter device to act on a decoded image.

4. A decoding device comprising:

the image filter device according to claim 2 , causing the image filter device to act on a decoded image.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2013
From: IKAI, TOMOHIRO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 030568/0344 →
Priority Claims (1)
JP 2010-278499 · Dec 14, 2010 · national
Continuity (1)
Related Publication 20130251051A1 · Sep 26, 2013