IP Library › Granted Patent US 9,608,055
Granted Patent B2
US 9,608,055 · App. 13/996,502 · Granted Mar 28, 2017

Semiconductor device having germanium active layer with underlying diffusion barrier layer

Inventors: Willy Rachmady (Beaverton, OR); Van H. Le (Portland, OR); Ravi Pillarisetty (Portland, OR); Jack T. Kavalieros (Portland, OR); Robert S. Chau (Beaverton, OR); Harold W. Kennel (Portland, OR)
Assignee: Intel Corporation
H01L29/0603B82Y10/00H01L21/28255H01L29/0607H01L29/1054H01L29/1083H01L29/165H01L29/66431H01L29/66439H01L29/775H01L29/7781H01L29/785H01L29/78603H01L29/78684
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Quick Facts
Patent No.
US 9,608,055
App. No.
13/996,502
Granted
Mar 28, 2017
Kind
B2
Abstract

Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

Claims (33)

1. A semiconductor device, comprising:

a gate electrode stack disposed above a substrate;

a germanium active layer disposed above the substrate, underneath the gate electrode stack;

a diffusion barrier layer disposed above the substrate, below the germanium active layer;

a junction leakage suppression layer disposed above the substrate, below the diffusion barrier layer;

a pair of recesses disposed in the germanium active layer and the diffusion barrier layer at respective sides of the gate electrode stack, the pair of recesses exposing an uppermost surface of the junction leakage suppression layer; and

epitaxial source and drain regions disposed in the pair of recesses and directly on the exposed uppermost surface of the junction leakage suppression layer and directly laterally adjacent to the germanium active layer and the diffusion barrier layer.

2. The semiconductor device of claim 1 , wherein the gate electrode stack is disposed directly on the germanium active layer, the germanium active layer is disposed directly on the diffusion barrier layer, the diffusion barrier layer is disposed directly on the junction leakage suppression layer.

3. The semiconductor device of claim 2 , further comprising:

a grading stack disposed directly between the substrate and the junction leakage suppression layer.

4. The semiconductor device of claim 1 , wherein the germanium active layer consists essentially of germanium, and the junction leakage suppression layer comprises phosphorous doped silicon germanium having a germanium to silicon ratio Si1-yGey.

5. The semiconductor device of claim 4 , wherein the diffusion barrier layer comprises silicon germanium having a germanium to silicon ratio Si1-xGex, where x is less than y.

6. The semiconductor device of claim 5 , wherein the diffusion barrier layer comprises silicon germanium having a germanium to silicon ratio Si1-xGex, where x is at least an order of magnitude less than y.

7. The semiconductor device of claim 4 , wherein the diffusion barrier layer consists essentially of silicon.

8. The semiconductor device of claim 4 , wherein the diffusion barrier layer impedes diffusion of phosphorous from the junction leakage suppression layer to the germanium active layer.

9. The semiconductor device of claim 1 , wherein the diffusion barrier layer is tensily stressed, and the germanium active layer is compressively stressed.

10. A semiconductor device, comprising:

a gate electrode stack disposed above a substrate;

a three-dimensional germanium active body disposed above and coupled with the substrate, underneath the gate electrode stack;

an isolation region disposed above the substrate and exposing the three-dimensional germanium active body;

a diffusion barrier layer disposed above the substrate, below the three-dimensional germanium active body;

a junction leakage suppression layer disposed above the substrate, below the diffusion barrier layer;

a pair of recesses disposed in the three-dimensional germanium active body and the diffusion barrier layer at respective sides of the gate electrode stack, the pair of recesses exposing an uppermost surface of the junction leakage suppression layer; and

epitaxial source and drain regions disposed in the pair of recesses and directly on the exposed uppermost surface of the junction leakage suppression layer and directly laterally adjacent to the three-dimensional germanium active body and the diffusion barrier layer.

11. The semiconductor device of claim 10 , wherein the gate electrode stack is disposed directly on the three-dimensional germanium active body, the three-dimensional germanium active body is disposed directly on the diffusion barrier layer, the diffusion barrier layer is disposed directly on the junction leakage suppression layer.

12. The semiconductor device of claim 11 , further comprising:

a grading stack disposed directly between the substrate and the junction leakage suppression layer.

13. The semiconductor device of claim 10 , wherein the three-dimensional germanium active body consists essentially of germanium, and the junction leakage suppression layer comprises phosphorous doped silicon germanium having a germanium to silicon ratio Si1-yGey.

14. The semiconductor device of claim 13 , wherein the diffusion barrier layer comprises silicon germanium having a germanium to silicon ratio Si1-xGex, where x is less than y.

15. The semiconductor device of claim 14 , wherein the diffusion barrier layer comprises silicon germanium having a germanium to silicon ratio Si1-xGex, where x is at least an order of magnitude less than y.

16. The semiconductor device of claim 13 , wherein the diffusion barrier layer consists essentially of silicon.

17. The semiconductor device of claim 13 , wherein the diffusion barrier layer impedes diffusion of phosphorous from the junction leakage suppression layer to the three-dimensional germanium active body.

18. The semiconductor device of claim 10 , wherein the diffusion barrier layer is tensily stressed, and the three-dimensional germanium active body is compressively stressed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2013
From: RACHMADY, WILLY; LE, VAN H.; PILLARISETTY, RAVI; KAVALIEROS, JACK T.; CHAU, ROBERT S.; KENNEL, HAROLD W.
To: INTEL CORPORATION
Reel/Frame 031214/0236 →
Continuity (1)
Related Publication 20140008700A1 · Jan 9, 2014