Digitally switched capacitor loop filter

1. A loop filter comprising:

a first loop filter input;

a second loop filter input;

a loop filter output coupled to the first loop filter input;

a loop filter capacitor coupled to the loop filter output and the first loop filter input;

sample switches coupled to the second loop filter input;

a voltage divider;

reset switches coupled to the voltage divider; and

switched capacitors coupled to the signal switches, the reset switches, the loop filter capacitor, and the loop filter output.

2. The loop filter of claim 1 , wherein the voltage divider comprises a resistive divider circuit that generates a reset direct current (DC) voltage.

3. The loop filter of claim 2 , wherein the reset DC voltage is substantially one half of a supply voltage.

4. The loop filter of claim 2 , wherein the reset DC voltage from the resistive divider circuit periodically resets the switched capacitors via the reset switches one switched capacitor at a time.

5. The loop filter of claim 1 , wherein the second loop filter input is applied to the switched capacitors via the sample switches one switched capacitor at a time.

6. The loop filter of claim 1 , wherein the first loop filter input is supplied by an integral charge pump and the second loop filter input is supplied by a proportional charge pump.

7. The loop filter of claim 6 , wherein the integral charge pump and the proportional charge pump receive signals from a phase frequency detector and wherein the loop filter output controls a voltage-controlled oscillator.

8. The loop filter of claim 6 ,

wherein the sample switches comprise:

a first sample switch including a first end coupled to the output of the proportional charge pump;

a second sample switch including a first end coupled to the output of the proportional charge pump;

wherein the reset switches comprise:

a first reset switch including a first end coupled to the voltage divider;

a second reset switch including a first end coupled to the voltage divider;

wherein switched capacitors comprise:

a first switched capacitor including (1) a first end coupled to (a) a second end of the first sample switch and (b) a second end of the first reset switch and (2) a second end coupled to the loop filter capacitor;

a second switched capacitor including (1) a first end coupled to (a) a second end of the second sample switch and (b) a second end of the second reset switch and (2) a second end coupled to the loop filter capacitor.

9. A phase lock loop comprising:

a phase frequency detector;

a first charge pump coupled to outputs of the phase frequency detector;

a second charge pump coupled to the outputs of the phase frequency detector;

a digitally switched loop filter comprising:

a loop filter capacitor;

digitally controlled sample switches coupled to an output of the second charge pump;

a voltage divider;

digitally controlled reset switches coupled to the voltage divider;

switched capacitors coupled to the sample switches, the reset switches, and the loop filter capacitor; and

a voltage-controlled oscillator including an input coupled to the loop filter capacitor, the switched capacitors, and an output of the first charge pump.

10. The phase lock loop of claim 9 , wherein the voltage divider comprises a resistive divider that generates a reset voltage.

11. The phase lock loop of claim 10 ,

wherein a signal from the output of the second charge pump is applied to the switched capacitors via the sample switches one switch capacitor at a time; and

wherein the reset voltage from the resistive divider periodically resets the switched capacitors via the reset switches one switched capacitor at a time.

12. The phase lock loop of claim 9 , wherein the first charge pump is an integral charge pump and the second charge pump is a proportional charge pump.

13. The phase lock loop of claim 9 ,

wherein the sample switches comprise:

a first sample switch including a first end coupled to the output of the second charge pump;

a second sample switch including a first end coupled to the output of the second charge pump;

wherein the reset switches comprise:

a first reset switch including a first end coupled to the voltage divider;

a second reset switch including a first end coupled to the voltage divider;

wherein switched capacitors comprise:

a first switched capacitor including (1) a first end coupled to (a) a second end of the first sample switch and (b) a second end of the first reset switch and (2) a second end coupled to the loop filter capacitor;

a second switched capacitor including (1) a first end coupled to (a) a second end of the second sample switch and (b) a second end of the second reset switch and (2) a second end coupled to the loop filter capacitor.

14. A method of filtering comprising:

providing inputs to first and second charge pumps;

charging a loop filter capacitor directly from the first charge pump;

charging the loop filter capacitor through two alternatively switched capacitors from the second charge pump;

alternatively resetting the two switched capacitors to a voltage supplied by a voltage divider;

providing a filtered output from the first charge pump, the loop filter capacitor, and the two switched capacitors.

15. The method of filtering of claim 14 , further comprising:

supplying a reference clock and a feedback clock as inputs to a phase frequency detector;

supplying up and down pulses generated by the phase frequency detector as the inputs to the first and second charge pumps.

16. The method of filtering of claim 14 , further comprising:

supplying the filtered output to a voltage-controlled oscillator.

17. The method of filtering of claim 14 , wherein the voltage divider comprises a resistive divider that generates a reset voltage that is supplied alternatively to the two switched capacitors via reset switches.

18. The method of filtering of claim 14 , wherein the first charge pump generates an integral signal that is supplied to the loop filter capacitor and wherein the second charge pump generates a proportional signal that is supplied alternatively to the two switched capacitors via sample switches.