Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.
1. A memory array comprising:
a plurality of paired-cell structures; each of the paired-cell structures comprising:
an electrically insulative projection between a pair of bottom electrodes;
programmable material extending across both bottom electrodes; and
a top electrode over the programmable material and extending across both bottom electrodes; and
wherein the bottom electrodes, programmable material and top electrode are comprised by two memory cells within the paired cell structures;
wherein the paired-cell structures are over a base comprising conductive contacts;
wherein the conductive contacts are electrically coupled with the bottom electrodes;
wherein each of the bottom electrodes has at least one segment which extends at angle of from greater than 30° to less than or equal to about 85° relative to a planar topography of the base;
wherein the to electrodes extend substantially parallel to the planar topography of the base and are in one-to-one correspondence with the paired-cell structures; and
wherein each of the bottom electrodes has two or more segments extending at different angles than one another relative to the planar topography of the base.
2. The memory array of claim 1 wherein the programmable material is comprised by straps that are in one-to-one correspondence with the paired-cell structures.
3. The memory array of claim 1 wherein the angle is within a range of from about 45° to about 60°.
4. The memory array of claim 1 wherein the bottom electrodes have thicknesses of less than or equal to about 3 nanometers.
5. The memory array of claim 1 wherein:
the base comprises buried wordlines;
the conductive contacts are source/drain regions paired with individual buried wordlines to form transistors; and
the memory cells of individual paired-cell structures are connected to source/drain regions of different transistors relative to one another.
6. The memory array of claim 5 wherein the memory cells are RRAM cells.