Manufacturing method of semiconductor structure
View Patent ↗A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps: providing an underlying layer; forming a tri-layered photoresist on the underlying layer, which comprises forming a bottom photoresist layer on the underlying layer, forming a silicon-containing material layer on the bottom photoresist layer, and forming a patterned photoresist layer on the silicon-containing material layer; performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and performing an etching process for forming a via hole, which comprises etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.
1. A manufacturing method of a semiconductor structure, comprising:
providing an underlying layer;
forming a tri-layered photoresist on the underlying layer, comprising:
forming a bottom photoresist layer on the underlying layer;
forming a silicon-containing material layer on the bottom photoresist layer; and
forming a patterned photoresist layer on the silicon-containing material layer;
performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and
performing an etching process for forming a via hole, comprising:
etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.
2. The manufacturing method according to claim 1 , wherein performing the etching process for forming the via hole further comprises:
etching the underlying layer according to the thin layer on the tri-layered photoresist.
3. The manufacturing method according to claim 2 , wherein etching the silicon-containing material layer is prior to etching the underlying layer.
4. The manufacturing method according to claim 1 , wherein the patterned photoresist layer has a first through hole with a first critical dimension (CD), and the thickness of the thin layer is determined according to the first critical dimension and an etching bias from the etching process.
5. The manufacturing method according to claim 1 , wherein the bottom photoresist layer comprises at least an etching resistive layer or an I-line photoresist.
6. The manufacturing method according to claim 1 , wherein the silicon-containing material layer is a silicon-containing hard-mask bottom anti-reflection coating (SHB).
7. The manufacturing method according to claim 1 , wherein the patterned photoresist is an ArF photoresist.
8. The manufacturing method according to claim 1 , wherein the thickness of the thin layer formed by the ALD process is equal to or less than 15 nm.
9. The manufacturing method according to claim 1 , further comprising: filling a conductive material into the via hole for forming a via contact.
10. The manufacturing method according to claim 1 , wherein providing the underlying layer comprises:
forming a diffusion barrier;
forming a dielectric layer on the diffusion barrier;
forming a SiON layer on the dielectric layer;
forming a patterned layer on the SiON layer; and
forming a cap oxide layer on the patterned layer.
11. A manufacturing method of a semiconductor structure, comprising:
providing an underlying layer;
forming a multi-layered photoresist on the underlying layer, comprising:
forming a hard mask layer on the underlying layer; and
forming a patterned photoresist layer on the hard mask layer;
performing a first etching process, comprising: etching the hard mask layer according to the patterned photoresist layer for forming a patterned hard mask layer;
performing an atomic layer deposition (ALD) process for forming a thin layer on the patterned hard mask layer; and
performing a second etching process for forming a via hole, comprising: etching the underlying layer according to the thin layer on the patterned hard mask layer.
12. The manufacturing method according to claim 11 , wherein the hard mask layer comprises at least one of a silicon-containing material layer, a bottom anti-reflective coating (BARC), or a bottom photoresist layer.
13. The manufacturing method according to claim 12 , wherein the bottom photoresist layer comprises at least an etching resistive layer or an I-line photoresist.
14. The manufacturing method according to claim 12 , wherein the silicon-containing material layer is a silicon-containing hard-mask bottom anti-reflection coating (SHB).
15. The manufacturing method according to claim 11 , wherein the patterned photoresist layer has a first through hole with a first critical dimension (CD), and the thickness of the thin layer is determined according to the first critical dimension and a first etching bias from the first etching process.
16. The manufacturing method according to claim 11 , wherein the patterned hard mask layer has a second through hole with a second critical dimension, and the thickness of the thin layer is determined according to the second critical dimension and a second etching bias from the second etching process.
17. The manufacturing method according to claim 11 , wherein the patterned photoresist is an ArF photoresist.
18. The manufacturing method according to claim 11 , wherein the thickness of the thin layer formed by the ALD process is equal to or less than 15 nm.
19. The manufacturing method according to claim 11 , further comprising: filling a conductive material into the via hole for forming a via contact.
20. The manufacturing method according to claim 11 , wherein providing the underlying layer comprises:
forming a diffusion barrier;
forming a dielectric layer on the diffusion barrier;
forming a SiON layer on the dielectric layer;
forming a patterned layer on the SiON layer; and
forming a cap oxide layer on the patterned layer.