Semiconductor device having metal gate and manufacturing method thereof

1. A method of manufacturing a semiconductor device having metal gate, comprising:

providing a substrate having at least a dummy gate formed thereon;

forming a sacrificial layer covering sidewalls of the dummy gate;

forming a dielectric layer exposing a top of the dummy gate after forming the sacrificial layer;

performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess; and

performing a second etching process to remove the dummy gate to form a second recess, the first recess and the second recess constructing a T-shaped gate trench.

2. The method of manufacturing a semiconductor device having metal gate according to claim 1 , further comprising at least a lightly-doped drain (LDD) formed in the substrate at two sides of the dummy gate.

3. The method of manufacturing a semiconductor device having metal gate according to claim 1 , further comprising following steps:

forming a spacer on the sidewalls of the dummy gate;

forming a source/drain in the substrate at two sides of the spacer;

removing a portion of the spacer; and

forming the sacrificial layer on the substrate.

4. The method of manufacturing a semiconductor device having metal gate according to claim 3 , wherein the sacrificial layer covering the source/drain.

5. The method of manufacturing a semiconductor device having metal gate according to claim 3 , wherein the sacrificial layer further comprises a strain stress layer or a contact etch stop layer (CESL).

6. The method of manufacturing a semiconductor device having metal gate according to claim 1 , further comprising following steps:

etching back the sacrificial layer to form a spacer on the sidewalls of the dummy gate;

forming a source/drain in the substrate at two sides of the spacer; and

forming the dielectric layer on the substrate.

7. The method of manufacturing a semiconductor device having metal gate according to claim 6 , wherein the sacrificial layer is formed not covering the source/drain.

8. The method of manufacturing a semiconductor device having metal gate according to claim 1 , wherein the first recess comprises a depth, and the depth has a range of 50-250 angstroms.

9. The method of manufacturing a semiconductor device having metal gate according to claim 1 , wherein an etching rate of the dielectric layer is different from an etching rate of the sacrificial layer.

10. The method of manufacturing a semiconductor device having metal gate according to claim 1 , wherein the sacrificial layer is exposed in a bottom of the first recess, and the dummy gate and the dielectric layer form sidewalls of the first recess.

11. The method of manufacturing a semiconductor device having metal gate according to claim 1 , further comprising a high-K gate dielectric layer exposed in a bottom of the second recess.

12. The method of manufacturing a semiconductor device having metal gate according to claim 1 , further comprising following steps performed after forming the second recess:

forming a work function metal layer and a filling metal layer in the T-shaped gate trench, sequentially; and

performing a planarization process to remove a portion of the work function metal layer and the filling metal layer to form a metal gate in the T-shaped gate trench.