Semiconductor device with reduced electrical resistance and capacitance
A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.
1. A semiconductor device comprising:
a first source/drain region;
a second source/drain region;
a channel region extending between the first source/drain region and the second source/drain region; and
a gate region comprising a gate electrode and a dielectric layer surrounding a circumference of the channel region, wherein:
a bottom surface of a first portion of the dielectric layer is separated a first distance from a top surface of the first source/drain region that underlies the dielectric layer by an insulator layer,
a bottom surface of a second portion of the dielectric layer is separated a second distance from the top surface of the first source/drain region by the insulator layer,
the second distance is different than the first distance,
the bottom surface of the first portion of the dielectric layer lies within a first plane and the bottom surface of the second portion of the dielectric layer lies within a second plane that is not co-planar with the first plane, and
a bottom surface of a third portion of the dielectric layer disposed diametrically opposite the first portion of the dielectric layer relative to the channel region is separated the first distance from the top surface of the first source/drain region by the insulator layer.
2. The semiconductor device of claim 1 , wherein the second portion of the dielectric layer is adjacent the channel region.
3. The semiconductor device of claim 1 , wherein the first source/drain region and the second source/drain region have a same conductivity type.
4. The semiconductor device of claim 1 , wherein a bottom surface of a fourth portion of the dielectric layer disposed diametrically opposite the second portion of the dielectric layer relative to the channel region is separated the second distance from the top surface of the first source/drain region by the insulator layer.
5. The semiconductor device of claim 1 , comprising:
a drift region overlying the channel region; and
a second insulator layer, wherein a first portion of the second insulator layer surrounds the drift region and extends between the drift region and a metal layer of the gate electrode.
6. The semiconductor device of claim 5 , wherein the drift region is in contact with the second insulator layer.
7. The semiconductor device of claim 1 , wherein:
the insulator layer abuts the first source/drain region to define a first interface,
the insulator layer abuts the first portion of the dielectric layer to define a second interface, and
the insulator layer abuts the second portion of the dielectric layer to define a third interface.
8. The semiconductor device of claim 7 , wherein a sidewall of the dielectric layer abuts a sidewall of the first source/drain region to define a fourth interface.