Apparatus and methods for leakage current reduction in integrated circuits
This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
1. An integrated circuit comprising:
a digital logic circuit having a plurality of inputs, wherein the digital logic circuit comprises a plurality of logic gates;
a first polarization circuit configured to receive a standby signal and a digital input signal comprising a plurality of bits, wherein when the standby signal is deactivated, the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit based on the digital input signal, and wherein when the standby signal is activated the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit; and
a first plurality of state elements, wherein the digital logic circuit is configured to generate a digital output signal and to provide the digital output signal to the first plurality of state elements,
wherein the integrated circuit is configured such that the first plurality of state elements are inhibited from loading a value of the digital output signal when the standby signal is activated.
2. The integrated circuit of claim 1 , wherein the low power state is associated with the smallest leakage current of the plurality of logic gates relative to all other states of the digital logic circuit.
3. The integrated circuit of claim 1 , wherein the plurality of logic gates comprises a plurality of standard cells.
4. The integrated circuit of claim 1 , wherein when the standby signal is deactivated, the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit by buffering the digital input signal.
5. The integrated circuit of claim 1 , wherein when the standby signal is deactivated, the first polarization circuit is configured to control the plurality of inputs of the digital logic circuit by inverting the digital input signal.
6. The integrated circuit of claim 1 , further comprising a second plurality of state elements configured to generate the digital input signal.
7. The integrated circuit of claim 6 , wherein a circuit layout of the first polarization circuit is integrated within a circuit layout of the second plurality of state elements.
8. The integrated circuit of claim 6 , wherein the second plurality of state elements comprise a plurality of flip-flops.
9. The integrated circuit of claim 1 , wherein the digital logic circuit comprises a combinational logic circuit.
10. The integrated circuit of claim 9 , wherein the digital logic circuit does not include any state elements.
11. The integrated circuit of claim 1 , wherein the first polarization circuit comprises a plurality of logic gates having a first input configured to receive the standby signal and a second input, wherein each second input of the plurality of logic gates of the first polarization circuit receives a different bit of the digital input signal.
12. The integrated circuit of claim 11 , wherein the plurality of logic gates of the first polarization circuit comprises at least one gate configured to generate a polarization bit based on a logical AND operation of a bit of the digital input signal and a logically inverted version of the standby signal.
13. The integrated circuit of claim 11 , wherein the plurality of logic gates of the first polarization circuit comprises at least one gate configured to generate a polarization bit based on a logical OR operation of a bit of the digital input signal and the standby signal.
14. The integrated circuit of claim 1 , wherein the digital logic circuit comprises two or more digital logic subcircuits including a first digital logic subcircuit and a second digital logic subcircuit, wherein the first polarization circuit is configured to control a plurality of inputs of the first digital logic subcircuit, and wherein a second polarization circuit is configured to control a plurality of inputs of the second digital logic subcircuit.
15. The integrated circuit of claim 1 , wherein the digital logic circuit comprises a subcircuit of a larger digital circuit.
16. An electronically-implemented method of leakage reduction in a digital circuit, the method comprising:
receiving a standby signal into a polarization circuit;
receiving a digital input signal into the polarization circuit;
controlling a plurality of inputs of a digital logic circuit based on the digital input signal using the polarization circuit when the standby signal is deactivated, the digital logic circuit comprising a plurality of logic gates;
controlling the plurality of inputs of the digital logic circuit to a low power state using the polarization circuit when the standby signal is activated, wherein the low power state is associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit;
generating a digital output signal using the digital logic circuit and providing the digital output signal to a plurality of state elements; and
inhibiting the plurality of state elements from loading a value of the digital output signal when the standby signal is activated.
17. The method of claim 16 , wherein controlling the plurality of inputs of the digital logic circuit to the low power state comprises controlling the plurality of inputs of the digital logic circuit to a state associated with the smallest leakage current of the plurality of logic gates relative to all other states of the digital logic circuit.
18. The method of claim 16 , wherein controlling the plurality of inputs of the digital logic circuit based on the digital input signal comprises buffering the digital input signal.
19. The method of claim 16 , wherein controlling the plurality of inputs of the digital logic circuit based on the digital input signal comprises inverting the digital input signal.
20. The method of claim 16 , wherein the digital logic circuit comprises a combinational logic circuit.