Lateral/vertical semiconductor device
A lateral semiconductor device and/or design including a space-charge generating layer and electrode located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
1. A method comprising:
designing a lateral semiconductor device comprising:
a device channel;
a first contact on a first end of the device channel;
a second contact on a second end of the device channel, wherein the second end is opposite the first end, and wherein the first and second contacts are located on a first side of the device channel;
a space-charge generating layer located on a second side of the device channel opposite the first side; and
an electrode electrically connected to the space-charge generating layer and located on an opposite side of the space-charge generating layer as the device channel, wherein the designing includes selecting a set of attributes for the space-charge generating layer such that the space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the first contact and the second contact; and
fabricating the lateral semiconductor device according to the design.
2. The method of claim 1 , wherein the selecting includes selecting a thickness of the space-charge generating layer to provide complete depletion of the device channel at a maximum operating voltage of the device and to prevent breakdown in the space-charge generating layer.
3. The method of claim 1 , wherein the selecting includes selecting a doping level and a doping profile in the space-charge generating layer to provide complete depletion of the device channel at a maximum operating voltage of the device.
4. The method of claim 1 , wherein the device is a field-effect transistor, the device further including at least one gate contact to the device channel located on the first side of the device channel, and wherein the space-charge generating layer includes an embedded region located under at least one of the at least one gate contact, wherein the selecting includes selecting a doping level in the embedded region to deplete the device channel under the at least one of the at least one gate contact at a zero gate bias.
5. The method of claim 1 , wherein the fabricating includes forming the second contact and the electrode such that the electrode is electrically connected to the second contact.
6. A lateral semiconductor device comprising:
a device channel;
a first contact on a first end of the device channel;
a second contact on a second end of the device channel, wherein the second end is opposite the first end, and wherein the first and second contacts are located on a first side of the device channel;
a space-charge generating layer located on a second side of the device channel opposite the first side; and
an electrode electrically connected to the space-charge generating layer and located on an opposite side of the space-charge generating layer as the device channel, wherein the space-charge generating layer has a set of attributes configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the first contact and the second contact.
7. The device of claim 6 , wherein the space-charge generating layer is configured such that the space-charge region completely depletes the device channel at a maximum operating voltage of the device.
8. The device of claim 6 , wherein the device is a diode.
9. The device of claim 6 , wherein the electrode is a non-ohmic contact to the space-charge generating layer.
10. The device of claim 6 , further comprising a barrier layer located between the space-charge generating layer and the electrode, wherein the barrier layer forms a p-n junction with the space-charge generating layer.
11. The device of claim 6 , wherein the space-charge generating layer has at least one of: a non-uniform doping or a non-uniform composition.
12. The device of claim 6 , wherein at least one of: the first contact or the second contact, is electrically connected to the electrode.
13. The device of claim 6 , wherein the device is a field-effect transistor, the device further including at least one gate contact to the device channel located on the first side of the device channel.
14. The device of claim 13 , wherein the space-charge generating layer includes an embedded region located under at least one of the at least one gate contact, wherein the embedded region is configured to deplete the device channel under the at least one of the at least one gate contact at a zero gate bias.
15. The device of claim 13 , wherein the first contact is a source contact topologically equivalent to a circle, wherein the second contact is a drain contact topologically equivalent to a ring, and wherein the at least one gate contact is topologically equivalent to a ring located between the first and second contacts.
16. The device of claim 13 , wherein the at least one gate is in the form of a V-groove.
17. A circuit comprising:
a lateral semiconductor device comprising:
a device channel;
a first contact on a first end of the device channel;
a second contact on a second end of the device channel, wherein the second end is opposite the first end, and wherein the first and second contacts are located on a first side of the device channel;
a space-charge generating layer located on a second side of the device channel opposite the first side; and
an electrode electrically connected to the space-charge generating layer and located on an opposite side of the space-charge generating layer as the device channel;
an input circuit electrically connected to the first contact; and
an output circuit electrically connected to the second contact, wherein the space-charge generating layer has a set of attributes configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the first contact and the second contact.
18. The circuit of claim 17 , wherein the device is a field-effect transistor, the device further including at least one gate contact to the device channel located on the first side of the device channel, and the circuit further including a control circuit electrically connected to the at least one gate contact.
19. The circuit of claim 18 , wherein the first contact comprises a source contact of the field-effect transistor and wherein the circuit is configured to apply a same voltage to the source contact and the electrode.
20. The circuit of claim 18 , wherein the space-charge generating layer includes an embedded region located under at least one of the at least one gate contact, wherein the embedded region is configured to deplete the device channel under the at least one of the at least one gate contact at a zero gate bias.