Integrated circuit having memory cell array including barriers, and method of manufacturing same

1. A method of manufacture of an integrated circuit device having a memory cell array including a plurality of memory cells, arranged in a matrix of rows and columns, wherein each of the plurality of memory cells includes at least one transistor having a gate, gate dielectric, and first, second, and body regions, the method comprising:

forming the first regions of the transistors in a semiconductor, wherein the first regions of the transistors of a first two adjacent memory cells are portions of a common first region that is shared between the transistors of the first two adjacent memory cells;

forming the second regions of the transistors in the semiconductor;

etching a trench in the common first region of the transistors of the first two adjacent memory cells to remove a portion of the common first region;

depositing a single solid barrier in the trench at a height substantially equivalent to a height of the common first region, wherein the barrier includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common first region, wherein the barrier is deposited via a single deposition process to fill the trench such that the barrier abuts only lateral portions of the first regions of the transistors of the first two adjacent memory cells and a top portion of an underlying insulating layer upon which the first, second, and body regions are formed, wherein the barrier has a depth substantially equal to a depth of the common first region; and

depositing an electrical contact directly on the common first region and the barrier, wherein the electrical contact serves as a common electrical contact to the first regions of the transistors of the first two adjacent memory cells.

2. The method of manufacture of claim 1 wherein the barrier includes one or more materials that are different from the material of the common first region.

3. The method of manufacture of claim 1 wherein the barrier includes one or more insulator, semiconductor and/or metal materials.

4. The method of manufacture of claim 1 wherein the barrier includes one or more materials having one or more crystalline structures that are different from the crystalline structure of the material of the common first region.

5. The method of manufacture of claim 1 the second regions of the transistors of a second two adjacent memory cells are portions of a common second region that is shared between the transistors of the second two adjacent memory cells, and wherein the method further includes:

etching a trench in the common second region of the transistors of the second two adjacent memory cells to remove a portion of the common second region; and

depositing a single second barrier in the trench, wherein the second barrier includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the second region.

6. The method of manufacture of claim 5 wherein the second barrier includes one or more materials that are different from the material of the common second region.

7. The method of manufacture of claim 5 wherein the second barrier includes one or more insulator, semiconductor and/or metal materials.

8. The method of manufacture of claim 7 wherein the second barrier includes one or more materials having one or more crystalline structures that are different from the crystalline structure of the material of the common second region.

9. The method of manufacture of claim 5 further including depositing an electrical contact on the common second region and the barrier which is disposed therein and/or therebetween.

10. A method of manufacture of an integrated circuit device having a memory cell array including a plurality of memory cells, arranged in a matrix of rows and columns, wherein each of the plurality of memory cells includes at least one transistor having a gate, gate dielectric, and first, second, and body regions, the method comprising:

forming the first regions of the transistors in a semiconductor layer that is disposed on or above an insulating layer or region, wherein the first regions of the transistors of a first two adjacent memory cells are portions of a common first region that is shared between the transistors of the first two adjacent memory cells;

forming the second regions of the transistors in the semiconductor layer that is disposed on or above the insulating layer or region;

etching a trench in the common first region of the transistors of the first two adjacent memory cells to remove a portion of the common first region;

depositing a single solid barrier in the trench at a height substantially equivalent to a height of the common first region, wherein the barrier provides a discontinuity in the common first region, wherein the barrier is deposited via a single deposition process to fill the trench such that the barrier abuts only lateral portions of the first regions of the transistors of the first two adjacent memory cells and a top portion of the underlying insulating layer upon which the first, second, and body regions are formed, wherein the barrier has a depth substantially equal to a depth of the common first region; and

depositing an electrical contact directly on the common first region and the barrier, wherein the electrical contact serves as a common electrical contact to the first regions of the transistors of the first two adjacent memory cells.

11. The method of manufacture of claim 10 wherein etching a trench in the common first region includes anisotropically etching the trench to remove a portion of the common first region.

12. The method of manufacture of claim 10 wherein:

etching a trench in the common first region includes anisotropically etching the trench to remove a portion of the common first region to expose a portion of the insulating layer or region; and

depositing the barrier in the trench includes depositing the barrier in the trench and on the exposed portion of the insulating layer or region.

13. The method of manufacture of claim 12 wherein the barrier includes one or more materials that are different from the material of the common first region.

14. The method of manufacture of claim 12 wherein the barrier includes one or more insulator, semiconductor and/or metal materials.

15. The method of manufacture of claim 12 wherein the barrier includes one or more materials having one or more crystalline structures that are different from the crystalline structure of the material of the common first region.

16. The method of manufacture of claim 10 wherein the second regions of the transistors of a second two adjacent memory cells are portions of a common second region, wherein the method further comprises:

etching a trench in the common second region of the transistors of the second two adjacent memory cells to remove a portion of the common second region; and

depositing a single second barrier in the trench, wherein the second barrier includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common second region.

17. The method of manufacture of claim 16 wherein the second barrier includes one or more materials that are different from the material of the common second region.

18. The method of manufacture of claim 16 wherein the second barrier includes one or more insulator, semiconductor, and/or metal materials.

19. The method of manufacture of claim 16 wherein the second barrier includes one or more materials having one or more crystalline structures that are different from the crystalline structure of the material of the common second region.

20. The method of manufacture of claim 10 wherein the body region of the transistor of each memory cell of the memory cell array is electrically floating, and wherein each memory cell is programmable to store one of a plurality of data states, each data state is representative of a charge in the body region of the associated transistor.