IP Library › Granted Patent US 9,142,658
Granted Patent B2
US 9,142,658 · App. 14/032,493 · Granted Sep 22, 2015

Compound semiconductor device and method of manufacturing the same

Inventors: Toshihide Kikkawa (Akiruno, JP); Kenji Nukui (Nakano, JP)
Assignee: Transphorm Japan, Inc.
H01L29/778H01L29/41725H01L29/42316H01L29/66431H01L29/66462H01L29/7787H01L29/2003
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Quick Facts
Patent No.
US 9,142,658
App. No.
14/032,493
Granted
Sep 22, 2015
Kind
B2
Abstract

A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons.

Claims (26)

1. A compound semiconductor device comprising:

a compound semiconductor layer; and

a pair of electrodes formed on an upper side the compound semiconductor layer,

wherein one of the pair of electrodes has three bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the three bottom surfaces are located at different distances from the transit electrons, with the bottom surface closest to the other of the pair of electrodes being more apart from the transit electrons; and wherein, in the one of the pair of electrodes, a side surface coupling predetermined adjacent two of the bottom surfaces out of the contact surfaces is in a tapered shape whose portion more apart from the other of the pair of electrodes becomes closer to the transit electrode.

2. The compound semiconductor device according to claim 1 , further comprising

a protective insulating film covering the compound semiconductor layer,

wherein, in the one of the pair of electrodes, a contact side surface close to the other of the pair of electrodes out of contact side surfaces with the protective insulating film is coupled to the bottom surface.

3. The compound semiconductor device according to claim 1 ,

wherein the compound semiconductor layer has an electron transit layer in which the transit electrons are generated and an electron supply layer formed above the electron transit layer, and

wherein the pair of electrodes are in contact with the electron supply layer and not in contact with the electron transit layer.

4. The compound semiconductor device according to claims 1 , further comprising:

another electrode formed between the pair of electrodes, above the compound semiconductor layer; and

a p-type semiconductor layer formed between the compound semiconductor layer and the other electrode.

5. A method of manufacturing a compound semiconductor device comprising:

forming a compound semiconductor layer; and

forming a pair of electrodes on an upper side the compound semiconductor layer,

wherein one of the pair of electrodes has three bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the three bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the other of the pair of electrodes being more apart from the transit electrons; and wherein, in the one of the pair of electrodes, a side surface coupling predetermined adjacent two of the bottom surfaces out of the contact surfaces is in a tapered shape whose portion more apart from the other of the pair of electrodes becomes closer to the transit electrode.

6. The method of manufacturing the compound semiconductor device according to claim 5 , further comprising

forming a protective insulating film covering the compound semiconductor layer,

wherein, in the one of the pair of electrodes, a contact side surface close to the other of the pair of electrodes out of contact side surfaces with the protective insulating film is coupled to the bottom surface.

7. The method of manufacturing the compound semiconductor device according to claim 5 ,

wherein the compound semiconductor layer has an electron transit layer in which the transit electrons are generated and an electron supply layer formed above the electron transit layer, and

wherein the pair of electrodes are in contact with the electron supply layer and not in contact with the electron transit layer.

8. The method of manufacturing the compound semiconductor device according to claim 5 , further comprising:

forming another electrode between the pair of electrodes, above the compound semiconductor layer; and

forming a p-type semiconductor layer between the compound semiconductor layer and the other electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2014
From: FUJITSU SEMICONDUCTOR LIMITED; FUJITSU LIMITED
To: TRANSPHORM JAPAN, INC.
Reel/Frame 032865/0218 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2013
From: KIKKAWA, TOSHIHIDE; NUKUI, KENJI
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 031373/0993 →
Priority Claims (1)
JP 2012-217346 · Sep 28, 2012 · national
Continuity (1)
Related Publication 20140091365A1 · Apr 3, 2014