Devices having nanoscale structures and methods for making same

1. A method for fabricating a semiconductor device, the method comprising:

forming a cavity in a substrate having a top surface, the cavity having vertical walls;

conformally depositing a thin layer of metal in the cavity on the substrate so as to form a metal thin film on the top surface and the walls of the cavity;

depositing a layer of insulation material on the metal thin film until the cavity is filled with the insulation material; and

planarizing the insulation material and the metal thin film on the top surface until the substrate is exposed and a top edge of the metal thin film deposited on the vertical walls is exposed and forms multiple exposed metal lines that are flush with the top surface of the substrate and that have substrate material on one side and the insulation material on the other side.

2. The method of claim 1 , wherein the width of the exposed metal lines is approximately 1 to 100 nanometers.

3. The method of claim 1 , wherein width of the exposed metal lines is approximately 1 to 10 nanometers.

4. The method of claim 1 , further comprising depositing a further insulation layer over the substrate, exposed metal lines, and insulation material in the cavity.

5. The method of claim 4 , wherein depositing a further insulation layer comprises depositing the further insulation layer using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition processes (ALD), or polymer spinning.

6. The method of claim 4 , wherein depositing a further insulation layer comprises depositing silicon oxide, aluminum oxide, hafnium dioxide, or titanium dioxide.

7. The method of claim 4 , further comprising etching the further insulation layer to form a dielectric pad that overlaps one of the metal lines.

8. The method of claim 4 , further comprising forming a metal electrode on the further insulation layer in a location in which the electrode overlaps one of the metal lines beneath the further insulation layer so as to form a metal-insulator-metal (MIM) tunneling diode in which the metal line is a bottom electrode of the MIM tunneling diode, the further insulation layer is an insulation layer of the MIM tunneling diode, and the metal electrode is a top electrode of the MIM tunneling diode.

9. The method of claim 1 , wherein forming a cavity comprises forming the cavity in the substrate using a lithographic process.

10. The method of claim 1 , wherein forming a cavity comprises forming the cavity in the substrate using dry etching.

11. The method of claim 1 , wherein conformally depositing a thin layer of metal comprise conformally depositing the thin layer of metal using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition processes (ALD).

12. The method of claim 1 , wherein conformally depositing a thin layer of metal comprise conformally depositing a thin layer of platinum, titanium, or nickel.

13. The method of claim 1 , depositing a layer of insulation material comprises depositing the layer of insulation material using chemical vapor deposition (CVD).

14. The method of claim 1 , wherein depositing a layer of insulation material comprises depositing a layer of amorphous silicon, silicon dioxide, silicon nitride, parylene, or polyimide.

15. The method of claim 1 , wherein planarizing the insulation material and the metal thin film comprises polishing the insulation material and the metal thin film.

16. The method of claim 1 , wherein the cavity has four vertical walls and wherein four exposed metal lines are formed.

17. The method of claim 16 , wherein the metal lines are connected to each other.