IP Library Granted Patent US 9,147,629
Granted Patent B2
US 9,147,629 · App. 14/032,696 · Granted Sep 29, 2015

Extremely thin package

Inventors: Chia Chuan Chen (Hsinchu County, TW); Lung-Pao Chin (Kaohsiung, TW); I-Kuo Lin (Hsinchu, TW)
Assignee: Silego Technology, Inc.
H01L23/3142H01L21/561H01L21/6836H01L23/49548H01L23/544H01L24/97H01L21/568H01L23/3107H01L2221/6834H01L2221/68327H01L2223/54433H01L2223/54486H01L2224/16245
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,147,629
App. No.
14/032,696
Granted
Sep 29, 2015
Kind
B2
Abstract

Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate.

Claims (25)

1. A device, comprising:

an integrated circuit connected to a leadframe or substrate via connections;

EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate; and

an adhesion film applied to a top-side of the device to protect the backside of the integrated circuit that is exposed.

2. The device of claim 1 , wherein during device assembly EMC between the backside of the integrated circuit and top-side of the device is removed.

3. The device of claim 1 , wherein during device assembly grinding is used to remove EMC from a top-side of the device and expose the backside of the integrated circuit.

4. The device of claim 3 , wherein grinding includes subjecting the leadframe or substrate to top-side grinding until the backside of the integrated circuit is exposed.

5. The device of claim 3 , wherein grinding includes subjecting the leadframe or substrate to top-side grinding until a desired package thickness is achieved.

6. The device of claim 1 , wherein the backside of the integrated circuit comprises exposed silicon.

7. The device of claim 3 , wherein grinding includes subjecting the leadframe or substrate to top-side grinding until a desired integrated circuit thickness is achieved.

8. The device of claim 1 , wherein the adhesion film is cured for improved adhesion to underlying EMC and the integrated circuit backside.

9. The device of claim 1 , wherein the device comprises an extremely thin DFN (dual flat no-lead) or QFN (quad flat no-lead) package.

10. The device of claim 1 , wherein the adhesion film protects the integrated circuit from light emission induced leakage and moisture penetration.

11. A method, comprising:

molding a device comprising an integrated circuit connected to a leadframe or substrate with EMC (Epoxy Molding Compound); and

grinding EMC on the device top-side to reduce device thickness.

12. The method of claim 11 , wherein grinding EMC on the device top-side includes grinding until a backside of the integrated circuit is exposed.

13. The method of claim 11 , wherein grinding EMC on the device top-side includes grinding a backside of the integrated circuit.

14. The method of claim 11 , wherein grinding EMC on the device top-side includes grinding the integrated circuit backside to achieve a prescribed integrate circuit thickness.

15. The method of claim 11 , wherein grinding EMC on the device top-side includes removing EMC between the backside of the integrated circuit and top-side of the device.

16. The method of claim 11 , further comprising applying an adhesion film to the device top-side to protect the integrated circuit.

17. The method of claim 16 , wherein the adhesion film protects an exposed backside of the integrated circuit.

18. The method of claim 16 , further comprising curing the adhesion film for improved adhesion to underlying EMC and the integrated circuit backside.

19. The method of claim 11 , wherein the device comprises an extremely thin DFN (dual flat no-lead) or QFN (quad flat no-lead) package.

20. The method of claim 11 , wherein the device comprises an exposed silicon extremely thin DFN (dual flat no-lead) or QFN (quad flat no-lead) package.

Assignments (2)
CHANGE OF NAME Recorded Nov 22, 2022
From: SILEGO TECHNOLOGY, INC.
To: RENESAS DESIGN TECHNOLOGY INC.
Reel/Frame 061987/0827 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2013
From: CHEN, CHIA CHUAN; CHIN, LUNG-PAO; LIN, I-KUO
To: SILEGO TECHNOLOGY, INC.
Reel/Frame 031754/0675 →
Continuity (2)
Provisional Application 61703708 · Sep 20, 2012
Related Publication 20140084429A1 · Mar 27, 2014