Multi-port semiconductor memory device with multi-interface

1. A semiconductor memory device comprising:

a first port configured to connect to a first processor by a first bus, and including a first interface circuit;

a second port configured to connect to a second processor by a second bus, and including a second interface circuit; and

a memory cell array including a first memory area connected to the first and second ports in common,

wherein the first memory area includes a plurality of magneto-resistive random access memory (MRAM) cells, and

wherein the first interface circuit is configured to convert first signals of the first bus, used in dynamic random access memory (DRAM) into second signals used in MRAM, and the second interface circuit is configured to convert third signals of the second bus, used in flash memory into fourth signals used in MRAM.

2. The semiconductor memory device of claim 1 , further comprising:

a control circuit connected to the memory cell array, and configured to adjust a number of memory cells included in the first memory area.

3. The semiconductor memory device of claim 1 , wherein each of the magneto-resistive random access memory cells is a spin transfer torque magneto-resistive random access memory (STT-MRAM) cell.

4. The semiconductor memory device of claim 1 , wherein the first signals of the first bus are DRAM interface signals used in a DRAM and the third signals of the second bus are flash memory interface signals used in either a NAND flash memory or a NOR flash memory.

5. The semiconductor memory device of claim 1 , wherein the memory cell array further comprises a second memory area connected to the first port and not the second port, and a third memory area connected to the second port and not the first port.

6. The semiconductor memory device of claim 1 , wherein the first processor is a baseband processor, and the second processor is an application processor.

7. The semiconductor memory device of claim 1 , further comprising:

a third port configured to connect to the second processor by a third bus, and including a third interface circuit,

wherein the first memory area is connected to the third port.

8. A mobile device comprising:

the semiconductor memory device of claim 7 ; and

a display unit configured to connect to the second processor,

wherein the semiconductor memory device is connected to the first and second processors.

9. The semiconductor memory device of claim 7 , wherein the third interface circuit is configured to receive signals used in DRAM.

10. A semiconductor memory device comprising:

a first port including a first interface circuit, and configured to connect to a first processor;

a second port including a second interface circuit, and configured to connect to a second processor; and

a memory cell array including a plurality of magneto-resistive random access memory (MRAM) cells, and divided into first through third memory areas,

wherein the first memory area is connected to the first port and not the second port and the second memory area is connected to the second port and not the first port,

wherein the third memory area is connected to the first and second ports,

wherein the first interface circuit is configured to convert signals used in dynamic random access memory (DRAM) into signals used in MRAM, and

wherein the second interface circuit is configured to convert signals used in flash memory into signals used in MRAM.

11. The semiconductor memory device of claim 10 , wherein each of the first through third memory areas includes a plurality of spin transfer torque magneto-resistive random access memory (STT-MRAM) cells arranged in a matrix of rows and columns.

12. The semiconductor memory device of claim 10 , further comprising:

a third port including a third interface circuit, and configured to connect to the second processor,

wherein the third memory area is connected to the third port, and

wherein the third interface circuit is configured to convert signals used in DRAM into signals used in MRAM.

13. A mobile device comprising:

the semiconductor memory device of claim 12 ; and

a display unit configured to connect to the second processor,

wherein the semiconductor memory device is connected to the first and second processors.

14. The semiconductor memory device of claim 10 , wherein the first processor is a baseband processor, and the second processor is an application processor for a multimedia device.

15. The semiconductor memory device of claim 10 , further comprising:

a control circuit connected to the memory cell array, and configured to adjust a number of memory cells included in the third memory area.

16. A multi processor system comprising:

first and second processors; and

a semiconductor memory device connected to the first and second processors by first and second buses,

wherein the semiconductor memory device comprises:

a first port configured to connect to the first processor by the first bus, and including a first interface circuit,

a second port configured to connect to the second processor by the second bus, and including a second interface circuit, and

a memory cell array including a first memory area connected to the first and second ports in common,

wherein the first memory area includes a plurality of magneto-resistive random access memory (MRAM) cells, and

wherein the first interface circuit is configured to convert first signals of the first bus, used in dynamic random access memory (DRAM) into second signals used in MRAM, and the second interface circuit is configured to convert third signals of the second bus, used in flash memory into fourth signals used in MRAM.

17. The multi processor system of claim 16 , wherein the semiconductor memory device further comprises:

a control circuit connected to the memory cell array, and configured to adjust a number of memory cells included in the first memory area.

18. The multi processor system of claim 16 , wherein the semiconductor memory device further comprises:

a third port configured to connect to the second processor by a third bus, and including a third interface circuit,

wherein the first memory area is connected to the third port.

19. The multi processor system of claim 16 , wherein the first processor is a baseband processor, and the second processor is an application processor.