IP Library Granted Patent US 9,023,681
Granted Patent B2
US 9,023,681 · App. 14/036,542 · Granted May 5, 2015

Method of fabricating heterojunction battery

Inventors: Xinwei Niu (Hangzhou, CN); Cao Yu (Hangzhou, CN); Lan Ding (Hangzhou, CN); Junmei Rong (Hangzhou, CN); Shiyong Liu (Hangzhou, CN); Minghua Wang (Hangzhou, CN); Jinyan Hu (Hangzhou, CN); Weizhi Han (Hangzhou, CN); Yongmin Zhu (Hangzhou, CN); Hua Zhang (Hangzhou, CN); Tao Feng (Hangzhou, CN); Jianbo Jin (Hangzhou, CN); Zhanwei Qiu (Hangzhou, CN); Liyou Yang (Hangzhou, CN)
Assignee: Chint Solar (Zhejiang) Co., Ltd.
H01L31/20
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,023,681
App. No.
14/036,542
Granted
May 5, 2015
Kind
B2
Abstract

The present invention discloses a method of fabricating a heterojunction battery, comprising the steps of: depositing a first amorphous silicon intrinsic layer on the front of an n-type silicon wafer, wherein the n-type silicon wafer may be a monocrystal or polycrystal silicon wafer; depositing an amorphous silicon p layer on the first amorphous silicon intrinsic layer; depositing a first boron doped zinc oxide thin film on the amorphous silicon p layer; forming a back electrode and an Al-back surface field on the back of the n-type silicon wafer; and forming a positive electrode on the front of the silicon wafer. In addition, the present invention further discloses a method of fabricating a double-sided heterojunction battery. In the present invention, the boron doped zinc oxide is used as an anti-reflection film in place of an ITO thin film; due to the special nature, especially the light trapping effect of the boron doped zinc oxide, the boron doped zinc oxide can achieve good anti-reflection. Therefore, the step of texturization is removed and the fabrication process simplified. As polycrystal silicon texturization is more challenging, the present invention is of more significance to heterojunction batteries using a polycrystal silicon wafer.

Claims (25)

1. A method of fabricating a heterojunction battery, comprising the steps of:

a) depositing a first amorphous silicon intrinsic layer on the front of an n-type silicon wafer;

b) depositing an amorphous silicon p layer on the first amorphous silicon intrinsic layer;

c) depositing a first boron doped zinc oxide thin film on the amorphous silicon p layer, wherein the range of the thickness of the first boron doped zinc oxide is between 500 nm and 1000 nm;

d) forming a back electrode and an Al-back surface field on the back of the n-type silicon wafer;

e) forming a positive electrode on the front of the n-type silicon wafer.

2. The method according to claim 1 , wherein the range of the thickness of the first amorphous silicon intrinsic layer is between 5 nm and 30 nm.

3. The method according to claim 1 , wherein the range of the thickness of the amorphous silicon p layer is between 5 nm and 30 nm.

4. A method of fabricating a double-sided heterojunction battery, comprising the steps of:

a) depositing a first amorphous silicon intrinsic layer on the front of an n-type silicon wafer;

b) depositing an amorphous silicon p layer on the first amorphous silicon intrinsic layer;

c) depositing a second amorphous silicon intrinsic layer on the back of the n-type silicon wafer;

d) depositing an amorphous silicon n layer on the second amorphous silicon intrinsic layer;

e) depositing a first boron doped zinc oxide thin film on the amorphous silicon p layer, and depositing a second boron doped zinc oxide thin film on the amorphous silicon n layer;

f) forming a back electrode on the back of the n-type silicon wafer;

g) forming a positive electrode on the front of the n-type silicon wafer.

5. The method according to claim 4 , wherein the range of the thickness of the first amorphous silicon intrinsic layer is between 5 nm and 30 nm.

6. The method according to claim 4 , wherein the range of the thickness of the amorphous silicon p layer is between 5 nm and 30 nm.

7. The method according to claim 4 , wherein the range of the thickness of the second amorphous silicon intrinsic layer is between 5 nm and 30 nm.

8. The method according to claim 4 , wherein the range of the thickness of the amorphous silicon n layer is between 5 nm and 30 nm.

9. The method according to claim 4 , wherein the range of the thickness of the boron doped zinc oxide is between 500 nm and 1000 nm.

10. The method according to claim 5 , wherein the range of the thickness of the boron doped zinc oxide is between 500 nm and 1000 nm.

11. The method according to claim 6 , wherein the range of the thickness of the boron doped zinc oxide is between 500 nm and 1000 nm.

12. The method according to claim 7 , wherein the range of the thickness of the boron doped zinc oxide is between 500 nm and 1000 nm.

13. The method according to claim 8 , wherein the range of the thickness of the boron doped zinc oxide is between 500 nm and 1000 nm.

Assignments (2)
CHANGE OF NAME Recorded May 10, 2022
From: CHINT SOLAR (ZHEJIANG) CO., LTD.
To: CHINT NEW ENERGY TECHNOLOGY CO., LTD.
Reel/Frame 059878/0848 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2013
From: NIU, XINWEI; YU, CAO; DING, LAN; RONG, JUNMEI; LIU, SHIYONG; MING, MINGHUA; HU, JINYAN; HAN, WEIZHI; ZHU, YONGMIN; ZHANG, HUA; FENG, TAO; JIN, JIANBO; QIU, ZHANWEI; YANG, LIYOU
To: CHINT SOLAR (ZHEJIANG)CO.,LTD.
Reel/Frame 031278/0212 →
Priority Claims (1)
CN 2013 1 0125902 · Apr 11, 2013 · national
Continuity (1)
Related Publication 20140308773A1 · Oct 16, 2014