STT-MRAM cell structures
View Patent ↗A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.
1. A method of fabricating a memory cell comprising:
forming a nonmagnetic bridge from a pinned layer to a first lateral edge of a free layer in the memory cell;
etching the memory cell to expose a second lateral edge of the free layer; and
forming an electrode making contact to the second lateral edge of the free layer.
2. The method, as set forth in claim 1 , wherein a current path is formed from the pinned layer, through the nonmagnetic bridge, laterally through the free layer, and to the electrode.
3. The method, as set forth in claim 1 , wherein forming a nonmagnetic bridge comprises forming using physical vapor deposition, chemical vapor deposition, conformal chemical vapor deposition, electroplating, or any other suitable deposition.
4. The method, as set forth in claim 1 , wherein etching the memory cell comprises dry etching.
5. The method, as set forth in claim 1 , comprising:
patterning the memory cell to reduce the size of the memory cell.
6. A method of fabricating a memory cell comprising:
forming a pinned ferromagnetic layer;
forming a dielectric layer on the pinned ferromagnetic layer;
forming a free ferromagnetic layer on the dielectric layer; and
forming a nonmagnetic bridge coupled to each of the pinned layer and the free layer.
7. The method, as set forth in claim 6 , comprising forming an antiferromagnetic layer beneath the pinned ferromagnetic layer.
8. The method, as set forth in claim 6 , comprising forming an electrode layer on the free ferromagnetic layer.
9. The method, as set forth in claim 6 , comprising:
forming a second dielectric layer on the free ferromagnetic layer; and
forming an electrode layer on the second dielectric later.
10. The method, as set forth in claim 6 , wherein forming the nonmagnetic bridge comprises forming the nonmagnetic bridge inside the dielectric layer.
11. The method, as set forth in claim 6 , wherein the forming the nonmagnetic bridge comprises surrounding the nonmagnetic bridge such that it surrounds the dielectric layer.
12. The method, as set forth in claim 6 , wherein forming the nonmagnetic bridge comprises forming a spacer in the dielectric layer.
13. The method, as set forth in claim 6 , wherein forming the nonmagnetic bridge comprises forming a conductive material.
14. The method, as set forth in claim 6 , comprising forming an access transistor electrically coupled to the memory cell and configured to provide electrical access to the memory cell.
15. The method, as set forth in claim 14 , further comprising:
coupling a gate of the access transistor to a word line of a memory array; and
electrically coupling the memory cell between a bit line and a source line to facilitate reading from and writing to the memory cell.