ELECTROSTATIC DISCHARGE (ESD) CIRCUITRY
Embodiments of the present disclosure describe electrostatic discharge (ESD) circuitry and associated techniques and configurations. In one embodiment, ESD circuitry includes a first node coupled with a supply voltage node and a ground node, a first transistor coupled with the first node and the supply voltage node, a second transistor coupled with the first node and the ground node, a second node coupled with the first transistor and the second transistor, a third transistor coupled with the second node and a third node coupled with the third transistor, wherein a first time period to charge the first node is less than a second time period to discharge the third node. Other embodiments may be described and/or claimed.
1 . Electrostatic discharge (ESD) circuitry comprising:
a first node coupled with a supply voltage node and a ground node;
a first transistor coupled with the first node and the supply voltage node;
a second transistor coupled with the first node and the ground node;
a second node coupled with the first transistor and the second transistor;
a third transistor coupled with the second node; and
a third node coupled with the third transistor, wherein a first time period to charge the first node is less than a second time period to discharge the third node.
2 . The ESD circuitry of claim 1 , further comprising:
a fourth transistor coupled with the third node, wherein the second time period to discharge the third node begins when the third transistor is set to an off-state and ends when the fourth transistor is set to an on-state.
3 . The ESD circuitry of claim 2 , wherein:
the first node is coupled with a gate of the first transistor and a gate of the second transistor;
the second node is coupled with a drain of the first transistor and a drain of the second transistor;
a source of the first transistor is coupled with the supply voltage node; and
a source of the second transistor is coupled with the ground node.
4 . The ESD circuitry of claim 3 , wherein:
the second node is coupled with a gate or base of the third transistor;
the third node is coupled with a source or emitter of the third transistor and a drain of the fourth transistor;
a drain or collector of the third transistor is coupled with the supply voltage node; and
a source of the fourth transistor is coupled with the ground voltage.
5 . The ESD circuitry of claim 2 , further comprising:
a fifth transistor coupled with the third node, wherein the third node is coupled with a gate of the fifth transistor;
a sixth transistor coupled with the fifth transistor, wherein a gate of the fifth transistor is coupled with a gate of the sixth transistor;
a seventh transistor coupled with the fifth transistor, wherein the gate of the fifth transistor is coupled with a gate of the seventh transistor; and
a latch node coupled with the sixth transistor, the seventh transistor and the fourth transistor, wherein the latch node is coupled with a drain of the sixth transistor, a drain of the seventh transistor and a gate of the fourth transistor.
6 . The ESD circuitry of claim 1 , wherein the second time period is at least seven times greater than the first time period.
7 . The ESD circuitry of claim 1 , wherein:
the first time period has a value less than 1 microsecond (μs); and
the second time period is greater than the first time period.
8 . The ESD circuitry of claim 1 , further comprising:
one or more resistors or capacitors coupled to one or both of the first node and the third node, wherein a resistance or capacitance of at least the first node or the third node is based on the one or more resistors or capacitors.
9 . The ESD circuitry of claim 1 , further comprising:
one or more additional transistors coupled with one or both of the first node and the third node, wherein a resistance or capacitance of at least the first node or the third node is based on the one or more additional transistors.
10 . The ESD circuitry of claim 1 , wherein the third transistor is a triple-well transistor or a silicon-on-insulator (SOI) transistor.
11 . A method of fabricating electrostatic discharge (ESD) circuitry comprising:
coupling a first node with a supply voltage node and a ground node;
coupling a first transistor with the first node and the supply voltage node;
coupling a second transistor with the first node and the ground node;
coupling a second node with the first transistor and the second transistor;
coupling a third transistor with the second node; and
coupling a third node with the third transistor, wherein a first time period to charge the first node is less than a second time period to discharge the third node.
12 . The method of claim 11 , further comprising:
coupling a fourth transistor with the third transistor, wherein the second time period to discharge the third node begins when the third transistor is set to an off-state and ends when the fourth transistor is set to an on-state.
13 . The method of claim 12 , wherein:
the first node is coupled with a gate of the first transistor and a gate of the second transistor;
the second node is coupled with a drain of the first transistor and a drain of the second transistor;
a source of the first transistor is coupled with the supply voltage node; and
a source of the second transistor is coupled with the ground node.
14 . The method of claim 13 , wherein:
the second node is coupled with a gate or base of the third transistor;
the third node is coupled with a source or emitter of the third transistor and a drain of the fourth transistor;
a drain or collector of the third transistor is coupled with the supply voltage node; and
a source of the fourth transistor is coupled with the ground voltage.
15 . The method of claim 12 , further comprising:
coupling a fifth transistor with the third node, wherein the third node is coupled with a gate of the fifth transistor;
coupling a sixth transistor with the fifth transistor, wherein a gate of the fifth transistor is coupled with a gate of the sixth transistor;
coupling a seventh transistor with the fifth transistor, wherein the gate of the fifth transistor is coupled with a gate of the seventh transistor; and
coupling a latch node with the sixth transistor, the seventh transistor and the fourth transistor, wherein the latch node is coupled with a drain of the sixth transistor, a drain of the seventh transistor and a gate of the fourth transistor.
16 . The method of claim 11 , wherein the second time period is at least seven times greater than the first time period.
17 . The method of claim 11 , wherein:
the first time period is less than 1 microsecond (μs); and
the second time period is greater than the first time period.
18 . The method of claim 11 , further comprising:
coupling one or more resistors or capacitors to one or both of the first node and the third node, wherein a resistance or capacitance of at least the first node or the third node is based on the one or more resistors or capacitors.
19 . The method of claim 11 , further comprising:
coupling one or more additional transistors with one or both of the first node and the third node, wherein a resistance or capacitance of at least the first node or the third node is based on the one or more additional transistors.
20 . A system comprising:
a power amplifier module including a die, the die including:
a power connection configured to provide a supply voltage node for operation of the die;
a ground connection configured to provide a ground node; and
an electrostatic discharge (ESD) clamp coupled with the supply voltage node and the ground node, the ESD clamp comprising:
a first node coupled with the supply voltage node and the ground node;
a first transistor coupled with the first node and the supply voltage node;
a second transistor coupled with the first node and the ground node;
a second node coupled with the first transistor and the second transistor;
a third transistor coupled with the second node; and
a third node coupled with the third transistor, wherein a first time period to charge the first node is less than a second time period to discharge the third node.
21 . The system of claim 20 , wherein the ESD clamp further comprises:
a fourth transistor coupled with the third transistor, wherein the second time period to discharge the third node begins when the third transistor is set to an off-state and ends when the fourth transistor is set to an on-state.