CLOCK DELAY DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME
Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.
1 . A clock delay detection circuit comprising:
a period signal generating unit configured to generate a counting control signal I;
a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal; and
a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein
the counting control signal has a period with a predetermined time.
2 . The clock delay detection circuit of claim 1 , wherein the predetermined time is n times a period of the clock, n being an integer greater than 1.
3 . The clock delay detection circuit of claim 1 , wherein the period signal generating unit includes:
a first delay unit configured to delay the counting control signal by a first delay time and to generate a first delay signal; and
a second delay unit configured to delay the first delay signal by a second delay time and to generate a second delay signal.
4 . The clock delay detection circuit of claim 3 , wherein a sum of the first delay time and the second delay time is n times a period of the clock, n being an integer greater than 1.
5 . The clock delay detection circuit of claim 3 , wherein the period signal generating unit further includes a triggering unit configured to receive the second delay signal and generate the counting control signal.
6 . The clock delay detection circuit of claim 1 , wherein the period signal dividing unit generates the counting enable signal by dividing the counting control signal by m, which is an integer greater than or equal to 2.
7 . The clock delay detection circuit of claim 1 , further comprising a clock dividing unit configured to divide the clock by m, which is an integer greater than or equal to 2, to generate a divided clock, wherein
the counting unit counts the counting enable signal with the divided clock.
8 . A clock delay detection circuit comprising:
a counting control unit configured to generate a counting control signal and a counting enable signal based on the counting control signal;
a first delay unit configured to delay the counting control signal and to generate a first delay signal; and
a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein
the counting control signal has a period with a predetermined time.
9 . The clock delay detection circuit of claim 8 , wherein the counting control unit includes a second delay unit configured to delay the first delay signal and to generate a second delay signal, and
wherein a sum of a delay amount of the first delay unit and the second delay unit is the predetermined time.
10 . The clock delay detection circuit of claim 8 , wherein the predetermined time is n times a period of the clock, n being an integer greater than 1.
11 . The clock delay detection circuit of claim 9 , wherein the counting control unit further includes:
a triggering unit configured to generate the counting control signal in response to the count start signal and the second delay signal; and
a period signal dividing unit configured to generate the counting enable signal by dividing the counting control signal.
12 . The clock delay detection circuit of claim 8 , further comprising a clock dividing unit configured to divide the clock by m, which is an integer greater than 2 to generate a divided clock, wherein
the counting unit counts the counting enable signal with the divided clock.
13 . A semiconductor apparatus comprising:
a delay-locked loop unit configured to delay an input clock and to generate a delay clock;
a counting control unit configured to generate a counting control signal and a counting enable signal based on the counting control signal, the counting enable signal being enabled with a duration longer than a predetermined time;
a command delay line configured to delay the counting control signal and to generate a delay command signal;
a counting unit configured to generate a delay information signal by counting the counting enable signal with the delay clock; and
an output control unit configured to generate an output control signal by delaying the delay command signal based on the delay information signal and a latency.
14 . The semiconductor apparatus of claim 13 , wherein the delay-locked loop unit includes a clock delay line configured to delay the input clock by the first delay time.
15 . The semiconductor apparatus of claim 13 , wherein the command delay line includes a command delay line configured to delay the counting control signal by the first delay time and to generate the delay command signal.
16 . The semiconductor apparatus of claim 15 , wherein the first delay time corresponds to a time interval of a delay that an external clock experiences in the device subtracted from n multiples of the input clock, n being greater than 1.
17 . The semiconductor apparatus of claim 15 , wherein the counting control unit includes:
a replica delay unit configured to delay the delay command signal by a second delay time and to generate a trigger signal;
a triggering unit configured to generate the counting control signal in response to the count start signal and the trigger control signal; and
a period signal dividing unit configured to generate the counting enable signal by dividing the counting control signal.
18 . The semiconductor apparatus of claim 17 , wherein the predetermined time is a sum of the first delay time and the second delay time.
19 . The semiconductor apparatus of claim 13 , wherein the output control unit includes:
a latency control unit configured to generate a corrected latency by subtracting a code value corresponding to the delay information signal from the latency; and
a shifting unit configured to generate the output enable signal by delaying the command delay signal by multiples of a clock that correspond to the corrected latency.
20 . A clock delay detection circuit comprising:
a period signal generating unit configured to generate an oscillating signal;
a period signal dividing unit configured to receive the oscillating signal to generate the counting enable signal; and
a counting unit configured to receive the counting enable signal and a clock and to generate a delay information signal.
21 . The clock delay detection circuit of claim 20 , wherein the oscillating signal has a period with a predetermined time.
22 . The clock delay detection circuit of claim 21 , wherein the counting enable signal has a duration longer than the predetermined time.
23 . The clock delay detection circuit of claim 20 , wherein the counting unit counts an enabled duration of the counting enable signal by using the clock and outputs the delay information signal as a result of the counting.
24 . The clock delay detection circuit of claim 23 , wherein the delay information signal is a code signal having information about a counted number.
25 . The clock delay detection circuit of claim 20 , further comprising:
a clock dividing unit configured to generated a divided clock by dividing the clock received by the counting unit.