NOR-type flash memory device configured to reduce program malfunction
Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof.
1. A NOR-type flash memory device comprising:
a memory array comprising at least one memory sector, wherein the at least one memory sector comprises a first sector bit line and a second sector bit line, wherein the memory array comprises a plurality of flash memory cells disposed on a matrix structure comprising a plurality of cell bit lines and a plurality of word lines arranged sequentially, and wherein the cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order;
a row selection circuit configured to be driven to select a word line in the plurality of word lines corresponding to a row address;
a column selection circuit configured to be driven to select a cell bit line in the plurality of cell bit lines corresponding to a column address; and
a program driver circuit configured to be driven to provide a program voltage to the selected cell bit line,
wherein the memory array comprises:
a first global switch configured to be driven to connect the first sector bit line to a global bit line;
a second global switch configured to be driven to connect the second sector bit line to the global bit line;
a first bias transistor configured to drive the first sector bit line to a first bias voltage; and
a second bias transistor configured to drive the second sector bit line to a second bias voltage,
the at least one memory sector comprises:
first connection switches configured to be driven to connect the first cell bit lines to the first sector bit line in response to column selection signals of the first cell bit lines; and
second connection switches configured to be driven to connect the second cell bit lines to the second sector bit line in response to column selection signals of the first cell bit lines,
the first connection switches are all turned on during the programming of a flash memory cell connected to any one of the second cell bit lines, and
the second connection switches are all turned on during the programming of a flash memory cell connected to any one of the first cell bit lines.
2. The device of claim 1 , wherein the at least one memory sector further comprises:
a cell region in which the flash memory cells are arranged;
a first connection region in which the first connection switches are arranged; and
a second connection region in which the second connection switches are arranged,
wherein the first connection region and the second connection region are disposed opposite each other across the cell region.
3. The device of claim 1 , wherein each of the first bias voltage and the second bias voltage is a ground voltage.