Semiconductor device having stacked chips
View Patent ↗According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.
1. A semiconductor device comprising:
a first chip; and
a second chip stacked with the first chip, the second chip including memory cell units and a memory logic unit between the memory cell units, the memory logic unit including a first line area and a second line area crossing each other to form a crossing area; and
bumps provided between the first chip and the memory logic unit of the second chip such that the bumps overlap the memory logic unit at the crossing area, and for communicating information between the first chip and the second chip.
2. The device of claim 1 , wherein
the bumps include a first bump for transferring a control signal and a second bump for transferring an address signal and data.
3. The device of claim 2 , wherein
the first bump is provided closer to a central portion of the second chip than the second bump.
4. The device of claim 2 , wherein
the first chip includes a first control signal line,
the second chip includes a second control signal line, and
the first control signal line is connected to the second control signal line through the first bump.
5. The device of claim 2 , further comprising:
a first electrode that passes through a semiconductor substrate of the second chip and that is connected to the first bump, and
a second electrode that passes through the semiconductor substrate and that is connected to the second bump.
6. The device of claim 2 , wherein
the first chip includes a first address bus, a first data bus, and a first multiplexer that selects one of the first address bus and the first data bus,
the second chip includes a second address bus, a second data bus, and a second multiplexer that selects one of the second address bus and the second data bus,
the first address bus selected by the first multiplexer is connected to the second address bus selected by the second multiplexer via the second bump, and
the first data bus selected by the first multiplexer is connected to the second data bus selected by the second multiplexer via the second bump.
7. The device of claim 6 , wherein
the first and second multiplexers select the first and second data buses after the first and second multiplexers select the first and second address buses in read and write operations of the second chip.
8. The device of claim 6 , wherein
each of the first and second data buses includes an input data bus and an output data bus,
the first multiplexer selects one of the input and output data buses, and
the second multiplexer selects the other one of the input and output data buses.
9. The device of claim 2 , wherein
the first chip is a processor chip generating the control signal and the address signal.
10. The device of claim 1 , wherein
the memory logic unit has an area that comprises first and second line areas crossing each other.
11. The device of claim 1 , wherein
the memory logic unit is provided at a center portion of the second chip, and
the memory cell units are provided symmetrically with respect to the center portion.
12. The device of claim 1 , wherein
one of the memory cell units is provided at a center portion of the second chip, and
the memory logic unit is provided around the center-portion memory cell unit.
13. The device of claim 1 , wherein
the second chip includes a cache memory.
14. The device of claim 1 , wherein
the second chip includes an MRAM.
15. The device of claim 1 , wherein
the memory logic unit includes a buffer and a decoder.
16. The device of claim 1 , wherein
the memory logic unit includes a cache logic circuit.