Techniques for providing a semiconductor memory device
View Patent ↗Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.
1. A method for biasing a semiconductor memory device comprising the steps of:
applying a first voltage potential to a first region of a first memory cell in an array of memory cells via a respective source line of the array;
applying a second voltage potential to a second region of the first memory cell via a respective bit line of the array;
applying a third voltage potential to a body region of the first memory cell via at least one respective word line of the array that is capacitively coupled to the body region; and
applying a fourth voltage potential to a third region of the first memory cell via a respective carrier injection line of the array;
wherein the first region, the second region, and the body region have a common first doping polarity.
2. The method according to claim 1 , further comprising increasing the third voltage potential applied to the at least one respective word line during a hold operation in order to perform a write logic low operation.
3. The method according to claim 1 , further comprising maintaining the first voltage potential, the second voltage potential, and the fourth voltage potential applied during a hold operation in order to perform a write logic low operation.
4. The method according to claim 1 , further comprising increasing the fourth voltage potential applied during a hold operation in order to perform a write logic high operation.
5. The method according to claim 1 , further comprising maintaining the first voltage potential, the second voltage potential, and the third voltage potential applied during a hold operation in order to perform a write logic high operation.
6. The method according to claim 1 , further comprising increasing the second voltage potential applied during a hold operation in order to perform a read operation.
7. The method according to claim 1 , further comprising increasing the third voltage potential applied during a hold operation in order to perform a read operation.
8. The method according to claim 1 , wherein the body region is disposed between the first region and the second region.
9. The method according to claim 1 , wherein the first region, the second region, and the body region have different doping concentrations.
10. The method according to claim 1 , wherein the third region has a second doping polarity that is different from the first doping polarity.
11. The method according to claim 10 , wherein the first region, the second region, and the body region are doped with donor impurities.
12. The method according to claim 11 , wherein the third region is doped with acceptor impurities.
13. The method according to claim 10 , wherein the first region, the second region, and the body region are doped with acceptor impurities.
14. The method according to claim 13 , wherein the third region is doped with donor impurities.
15. The method according to claim 1 , wherein the first region, the second region, and the body region are undoped regions.
16. The method according to claim 1 , wherein the first region, the second region, the body region, and the third region are arranged in a planar configuration.
17. The method according to claim 1 , wherein the first region, the second region, the body region, and the third region are arranged in a vertical configuration.
18. The method according to claim 17 , wherein the source line and the bit line are arranged on opposite sides of the memory cell.
19. The method according to claim 17 , wherein the word line is arranged on at least two opposing sides of the memory cell.