Memory device with die stacking and heat dissipation
A memory device with die stacking is provided. A plurality of substrates layers are stacked together into a stack. Each substrate layer may include a substrate having a plurality of cavities to receive integrated circuit components within the thickness of the substrate. A plurality of conductive spheres are arranged between at least two adjacent substrate layers and are electrically coupled to the integrated circuit components in at least one of the two adjacent substrates. The two adjacent substrate layers of the stack include: (a) a first substrate having a first plurality of cavities to receive integrated circuit components, and (b) a second substrate having a second plurality of cavities to receive integrated circuit components, wherein the first plurality of cavities is offset from a second plurality of cavities.
1. A memory stack, comprising:
a plurality of substrate layers stacked together into a stack, each substrate layer including a substrate having a plurality of cavities to receive integrated circuit components within the thickness of the substrate, each substrate having a first surface configured to couple to a first plurality of integrated circuits received in a corresponding number of cavities and a second surface configured to couple to a second plurality of integrated circuits received in the corresponding number of cavities, wherein the first and second surfaces are on opposing sides of the substrate;
a plurality of conductive spheres arranged between at least two adjacent substrate layers and electrically coupled to the integrated circuit components in at least one of the two adjacent substrates; and
at least two integrated circuit components mounted in each cavity of a substrate layer.
2. The memory stack of claim 1 , wherein the plurality of conductive spheres includes
a first plurality of conductive spheres between a first set of adjacent substrates of the stack,
a second plurality of conductive spheres between a second set of adjacent substrates of the stack, wherein the first plurality of conductive spheres is electrically coupled to the second plurality of conductive spheres.
3. The memory stack of claim 1 , wherein two adjacent substrate layers of the stack include:
a first substrate having a first plurality of cavities to receive integrated circuit components, and
a second substrate having a second plurality of cavities to receive integrated circuit components, wherein the first plurality of cavities is offset from a second plurality of cavities.
4. The memory stack of claim 1 , further comprising the first plurality of integrated circuit components and the second plurality of integrated circuit components, wherein the first and second pluralities of integrated circuit components are stacked as pairs within a corresponding number of the plurality of cavities of the substrate, and coupled to respective first and second surfaces of the substrate.
5. The memory stack of claim 4 , wherein adjacent opposing surfaces of the first and second integrated circuits are positioned within the cavity and between the first and second surfaces of the substrate.
6. The memory stack of claim 1 , further comprising:
a plurality of passive components received within a subset of the plurality of cavities.
7. The memory stack of claim 4 , wherein the first and second integrated circuit components are packaged integrated circuit components, each having connection leads or legs bent for surface mounting the packaged components in a first orientation, wherein the packaged components are mounted on the substrate a second orientation that is inverted with respect to the first orientation.
8. The memory stack of claim 1 , wherein the thickness of each substrate is in the range of 40 to 100 mils.
9. The memory stack of claim 1 , further comprising:
a cavity within one of the substrates; and
an electronic component within the cavity, wherein the electronic component is thicker than the space between two adjacent substrates.
10. A memory module, comprising:
a substrate having a plurality of memory devices on at least one side of the substrate;
an electrical bus interface along one edge of the substrate;
one or more ground planes embedded within the substrate and extending to one or more edges of the substrate;
one or more signal planes embedded within the substrate; and
an external layer of heat conductive material plated onto at least three edge surfaces of the substrate.
11. The memory module of claim 10 , wherein the external layer of heat conductive material is coupled to the ground planes and isolated from the signal planes.
12. The memory module of claim 10 , wherein the external layer of heat conductive material transfers heat away from the memory module.
13. The memory module of claim 10 , wherein the heat conductive material is metal.
14. The memory module of claim 11 , wherein the coupling is an electrical coupling.