Trench formation with CD less than 10 NM for replacement Fin growth
Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.
1. A method of forming a semiconducting fin structure, comprising:
etching a silicon layer to form a feature bounded by an insulator material;
conformally depositing a dielectric layer over the insulator material and the feature formed in the silicon layer;
etching the dielectric layer to expose a portion of the silicon layer within the feature through the dielectric layer;
forming a semiconducting material on the exposed portion of the silicon layer, the semiconducting material filling the feature between the dielectric layer; and
removing a portion of the dielectric layer, the insulator material and the semiconducting material to form a planar surface.
2. The method of claim 1 , further comprising etching a first region of a photoresist layer to expose a first region of a neutral layer.
3. The method of claim 2 , further comprising etching the exposed region of the neutral layer to expose a first region of a hardmask layer.
4. The method of claim 3 , further comprising etching the exposed region of the hardmask layer to expose a first region of the silicon layer.
5. The method of claim 4 , further comprising etching a second region of the photoresist layer and a second region of the neutral layer to expose a second region of the hardmask layer.
6. The method of claim 5 , further comprising etching the first region of the silicon layer to form a trench.
7. The method of claim 6 , further comprising depositing the insulator material in the trench.
8. The method of claim 7 , further comprising planarizing the second region of the hardmask layer and the insulator material.
9. The method of claim 8 , further comprising implanting ions into a second region of the silicon layer and the insulator material.
10. The method of claim 9 , further comprising etching the second region of the hardmask layer to expose the second region of the silicon layer.
11. The method of claim 1 , wherein the semiconducting material has a critical dimension of less than about 10 nm.
12. The method of claim 11 , wherein the semiconducting material comprises a III-V material.
13. A method of forming a semiconducting fin structure, comprising:
etching a silicon layer to form a feature bounded by an oxide material, wherein the feature has an aspect ratio of between about 5:1 and about 30:1;
conformally depositing by atomic layer deposition or chemical vapor deposition a dielectric layer over the oxide material and the feature formed in the silicon layer;
etching the dielectric layer to expose a portion of the silicon layer within the feature through the dielectric layer;
forming a material comprising silicon and germanium on the exposed portion of the silicon layer, the silicon and germanium filling the feature between the dielectric layer; and
removing a portion of the dielectric layer, the oxide material and the silicon and germanium to form a planar surface.
14. The method of claim 13 , wherein the material comprising silicon and germanium has a critical dimension of less than about 10 nm.
15. A method of forming a semiconducting fin structure, comprising:
etching a first region of a photoresist layer to expose a first region of a neutral layer;
etching the exposed region of the neutral layer to expose a first region of a hardmask layer;
etching the exposed region of the hardmask layer to expose a first region of a silicon layer;
etching a second region of the photoresist layer and a second region of the neutral layer to expose a second region of the hardmask layer;
etching the first region of the silicon layer to form a trench;
depositing an insulator material in the trench;
planarizing the second region of the hardmask layer and the insulator material;
implanting ions into the silicon layer and the insulator material;
etching the second region of the hardmask layer to expose a second region of the silicon layer;
etching a portion of the insulator material to level the insulator material with the second region of the silicon layer;
etching the second region of the silicon layer to a depth of the implanted ions to expose insulator features;
conformally depositing a dielectric layer over the second region of the silicon layer and the insulator features;
etching the dielectric layer from a top portion of the insulator features and a portion of the second region of the silicon layer to form a regrowth region;
depositing a semiconducting material on the regrowth region to form a fin structure, wherein the dielectric layer is disposed between the fin structure and the insulator material; and
removing a portion of the dielectric layer, the insulator material and the fin structure to form a planar surface.
16. The method of claim 15 , wherein the first region and second region of the photoresist material comprise PMMA and polysilicon, respectively.
17. The method of claim 15 , wherein the neutral layer comprises an antireflective material.
18. The method of claim 15 , wherein the hardmask layer comprises silicon nitride.
19. The method of claim 15 wherein the fin structure has an aspect ratio between about 5:1 and about 30:1.
20. The method of claim 19 , wherein the fin structure has a critical dimension of less than about 10 nm.