Semiconductor device including FinFET device
A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
1. An apparatus, comprising, comprising:
a memory element having two terminals;
a source line, extending in a first direction above the surface of a substrate;
a pair of fins, extending in parallel in a second direction above the surface of the substrate, each of the fins being partially wrapped around by the source line;
a local interconnect extending in the first direction above the surface of the substrate, contacting one terminal of the memory element, and partially wrapping around the pair of fine;
a gate line extending in the first direction above the surface of the substrate, arranged between the source line and the local interconnect, and partially wrapping around the pair of the fins; and
a bit line coupled to another terminal of the memory element, and extending in the second direction above the substrate, but not in contact with the source line and the gate line.
2. The apparatus of claim 1 , wherein the memory element is a NVM.
3. The apparatus of claim 1 , wherein the memory element is selected from the group of elements consisting of PCRAM, MRAM, CMRAM, and FeRAM.
4. The apparatus of claim 1 , wherein the local interconnect is made of a conductive material.
5. The apparatus of claim 1 , wherein the local interconnect is made of a conductive material selected from the one or more of copper, silver, gold, aluminum, and their alloys.
6. A memory device, comprising:
a memory element;
a pair of fins extending in parallel;
a gate line coupled to each of the pair of fins; and
a local interconnect coupled between the memory element and the pair of fins, the local interconnect being in direct contact with a top surface of each of the pair of fins.
7. The memory device of claim 6 , wherein the local interconnect directly contacts a sidewall of each of the pair of fins.
8. The memory device of claim 6 , wherein the local interconnect directly contacts a first sidewall and a second sidewall of each of the pair of fins.
9. The memory device of claim 6 , wherein the memory element is a NVM.
10. The memory device of claim 6 , wherein the memory element is selected from the group consisting of PCRAM, MRAM, CBRAM, and FeRAM.
11. The memory device of claim 6 , wherein the local interconnect is made of a conductive material.
12. The memory device of claim 6 , wherein the local interconnect is made of a conductive material selected from one or more of copper, silver, gold, aluminum, and their alloys.
13. The memory device of claim 6 , wherein the local interconnect partially wraps around each of the pair of fins.
14. A FinFET device, comprising:
a pair of fins extending in parallel;
a gate line coupled to each of the pair of fins; and
a local interconnect in direct contact with a top surface of each of the pair of fins.
15. The FinFET device of claim 14 , wherein the local interconnect directly contacts a sidewall of each of the pair of fins.
16. The FinFET device of claim 14 , wherein the local interconnect directly contacts a first sidewall and a second sidewall of each of the pair of fins.
17. The FinFET device of claim 14 , wherein the local interconnect partially wraps around each of the pair of fins.
18. The FinFET device of claim 14 , wherein the local interconnect is coupled to a drain region of each of the pair of fins.
19. The FinFET device of claim 14 , wherein the local interconnect is made of a conductive material.
20. The FinFET device element of claim 14 , wherein the local interconnect is made of a conductive material selected from one or more of copper, silver, gold, aluminum, and their alloys.
21. A memory device, comprising:
a memory element;
a pair of fins extending in parallel;
a gate line coupled to each of the pair of fins; and
a local interconnect coupled between the memory element and the pair of fins, the local interconnect being in direct contact with each of the pair of fins, the local interconnect partially wrapping around each of the pair of fins.
22. The memory device of claim 21 , wherein the memory element is a NVM.
23. The memory device of claim 21 , wherein the memory element is selected from the group consisting of PCRAM, MRAM, CBRAM, and FeRAM.
24. The memory device of claim 21 , wherein the local interconnect is made of conductive material.
25. The memory device of claim 21 , wherein the local interconnect is made of a conductive material selected from one or more of copper, silver, gold, aluminum, and their alloys.
26. A FinFET device, comprising:
a pair of fins extending in parallel;
a gate line coupled to each of the pair of fins; and
a local interconnect in direct contact with each of the pair of fins, the local interconnect partially wrapping around each of the pair of fins.
27. The FinFET device of claim 26 , wherein the local interconnect is made of conductive material.
28. The FinFET device of claim 26 , wherein the local interconnect is made of a conductive material selected from one or more of copper, silver, gold, aluminum, and their alloys.