Mergeable semiconductor device with improved reliability
View Patent ↗A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
1. A device comprising:
a semiconductor substrate;
source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another; and
a composite body region disposed in the semiconductor substrate, having a second conductivity type, and in which a channel during operation is formed for charge carriers flowing from the source region to the drain region, the composite body region comprising a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region;
wherein the drain region is disposed in the second well region such that the charge carriers flow from the first well region into the second well region to reach the drain region; and
wherein the second well region includes dopant of the first conductivity type to have a lower net dopant concentration level of the second conductivity type than the first well region.
2. The device of claim 1 , further comprising:
a drain extension region disposed adjacent the drain region, having the first conductivity type, and through which the charge carriers pass after exiting the channel; and
a pocket disposed within the drain extension region, having the second conductivity, and configured to establish a depletion region along an edge of the drain region.
3. The device of claim 2 , wherein the pocket is disposed at a surface of the semiconductor substrate.
4. The device of claim 2 , wherein the drain extension region is disposed within the second well region.
5. The device of claim 2 , further comprising a gate structure supported by the semiconductor substrate between the source and drain regions, wherein the pocket is disposed along an edge of the gate structure.
6. The device of claim 1 , further comprising:
an isolation ring disposed in the semiconductor substrate within which the device is disposed; and
further source and drain regions disposed in the semiconductor substrate within the isolation ring, having the first conductivity type, and laterally spaced from one another;
wherein:
a further channel is formed in the composite body region for further charge carriers flowing from the further source region to the further drain region during operation;
the first well region of the composite body region extends laterally across the further source and drain regions;
the composite body region further comprises a third well region disposed in the first well region;
the further drain region is disposed on the third well region such that the further charge carriers in the further channel flow from the first well region into the third well region to reach the further drain region; and
wherein the third well region has a lower dopant concentration level than the first well region.
7. The device of claim 6 , wherein the isolation ring comprises:
a buried insulator layer in the semiconductor substrate that extends laterally across and under an entire extent of the composite body region; and
a deep trench isolation (DTI) ring that defines a lateral periphery of the composite body region and that extends from a surface of the semiconductor substrate to reach the buried insulator layer.
8. The device of claim 6 , wherein:
the composite body region further comprises a body contact region in the first well region; and
the first-named channel and the further channel are symmetrically disposed about the body contact region.
9. The device of claim 1 , wherein the semiconductor substrate comprises a base substrate, a buried insulator layer on the base substrate, and a semiconductor layer on the buried insulator layer in which the source, drain, and composite body regions are disposed.
10. A device comprising:
a semiconductor substrate;
source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another;
a gate structure supported by the semiconductor substrate between the source and drain regions;
a composite body region disposed in the semiconductor substrate, having a second conductivity type, and in which a channel is formed under the gate structure for charge carriers flowing from the source region to the drain region during operation;
a drain extension region disposed adjacent the drain region, having the first conductivity type, and through which the charge carriers pass after exiting the channel; and
a pocket in the drain extension region, having the second conductivity type, and configured to establish a depletion region along an edge of the gate structure;
wherein the composite body region comprises a first well region and a second well region disposed within the first well region, the second well region having a lower net dopant concentration level of the second conductivity type than the first well region.
11. The device of claim 10 , wherein the pocket is disposed at a surface of the semiconductor substrate.
12. The device of claim 10 , wherein the first well region extends laterally across the source and drain regions.
13. The device of claim 12 , wherein the drain extension region is disposed within the second well region.
14. The device of claim 10 , further comprising:
an isolation ring disposed in the semiconductor substrate within which the device is disposed;
further source and drain regions disposed in the semiconductor substrate within the isolation ring, having the first conductivity type, and laterally spaced from one another;
a further gate structure supported by the semiconductor substrate between the further source and drain regions;
a further drain extension region disposed adjacent the further drain region, having the first conductivity type, and through which the charge carriers pass after exiting a further channel formed in the composite body region for further charge carriers flowing from the further source region to the further drain region during operation; and
a further pocket in the further drain extension region, having the second conductivity type, and configured to establish a further depletion region along an edge of the further gate structure.
15. The device of claim 1 , wherein the first and second well regions are positioned such that, during operation, first and second channel regions of the channel are established in the first and second well regions, respectively.
16. The device of claim 10 , wherein the second well region laterally overlaps the gate structure such that, during operation, first and second channel regions of the channel are established in the first and second well regions, respectively.
17. The device of claim 10 , wherein the first well region extends across an entire lateral extent of the source region and an entire lateral extent of the drain region.
18. A device comprising:
a semiconductor substrate;
source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another;
a gate structure supported by the semiconductor substrate between the source and drain regions; and
a composite body region disposed in the semiconductor substrate, having a second conductivity type, and comprising a first well region and a second well region disposed within the first well region, the second well region having a lower net dopant concentration level of the second conductivity type than the first well region;
wherein the second well region laterally overlaps the gate structure such that, during operation, first and second channel regions are established in the first and second well regions, respectively, for charge carriers flowing from the source region to the drain region.
19. The device of claim 18 , wherein the first well region extends across an entire lateral extent of the source region and an entire lateral extent of the drain region.
20. The device of claim 18 , wherein:
the second well region is counter-doped with dopant of the first conductivity type, the dopant of the first conductivity type comprising phosphorus dopant;
the composite body region includes boron dopant as dopant of the second conductivity type; and
the gate structure comprising a gate oxide layer such that, at an interface between the gate oxide layer and the semiconductor substrate, a deficiency in the boron dopant and a pile-up of the phosphorus dopant are present.