Patent Assignment
Reel/Frame 037785/0454
Corrective Assignment of Incorrect Patent Application Number 14085520 ,Previously Recorded at Reel: 037458 Frame: 0399. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Recorded: 2016-02-11
Pages: 19
Assignor
CITIBANK, N.A.
Executed: 2015-12-07
Assignee
MORGAN STANLEY SENIOR FUNDING, INC.
1300 THAMES STREET, 4TH FLOOR, BALTIMORE, MARYLAND, 21231
Covered Properties
(144)
Electronic Device and Method
Pressure Sensor Having Multiple Pressure Cells and Sensitivity Estimation Methodology
Variable Reluctance Sensor Interfaces and Methods of Their Operation
Variable Reluctance Sensor Interfaces with Signal Pre-Processing and Methods of Their Operation
Power Amplifiers with Signal Conditioning
Method and Apparatus for Dynamic Resource Partition in Simultaneous Multi-Thread Microprocessor
Semiconductor Device with Buried Conduction Path
Mergeable Semiconductor Device with Improved Reliability
Techniques for Generating Bit Log-Likelihood Ratios in Communication Systems Using Differential Modulation
Detecting Repeated Preamble Symbols Using Over-Sized Discrete Fourier Transforms
Non-Volatile Memory (Nvm) with Imminent Error Prediction
Method of Gate Strapping in Split-Gate Memory Cell with Inlaid Gate
Patent:
8,969,940 →
Application:
14/048,570 →
Heat Conductive Substrate for Integrated Circuit Package
Sector-Based Regulation of Program Voltages for Non-Volatile Memory (Nvm) Systems
System for Reducing Leakage Power of Electronic Circuit
Patent:
8,762,922 →
Application:
14/052,764 →
Mems Sensor Device with Multi-Stimulus Sensing and Method of Fabrication
Application:
14/053,236 →
Publication:
US 2015/0102437
ESD Protection with Asymmetrical Bipolar-Based Device
Detecting Byte Ordering Type Errors in Software Code
Shielded Device Packages and Related Fabrication Methods
Application:
14/056,644 →
Publication:
US 2015/0108621
Microelectronic Packages Containing Stacked Microelectronic Devices and Methods for the Fabrication Thereof
Coated Lead Frame Bond Finger
Sensor Device Packages and Related Fabrication Methods
Traceability for Automated Staining System
Semiconductor Device Including an Active Region and Two Layers Having Different Stress Characteristics
Method of Adding Features to Parameterized Cells
Patent:
8,954,903 →
Application:
14/064,225 →
Devices and Methods of Operation for Separating Semiconductor Die from Adhesive Tape
Die Crack Detector with Integrated One-Time Programmable Element
Signal Error Compensation for a Magnetometer in a Sensor Package
Application:
14/065,059 →
Publication:
US 2015/0115936
Method, Apparatus, and Computer-Readable Recording Medium for Recognizing Fingerprint
Adaptive Adjustment of Power Splitter
Injection of a Chemical Reagent into a Process Stream That Contains Lignin
System for Placing Dummy Tiles in Metal Layers of Integrated Circuit Design
Patent:
8,898,612 →
Application:
14/066,696 →
Body Bias Control Circuit
Microelectronic Packages Having Layered Interconnect Structures and Methods for the Manufacture Thereof
Functional Path Failure Monitor
Watchpoint Support System for Functional Simulator
Digital Calibration of Programmable Gain Amplifiers
Semiconductor Device Packages Using a Thermally Enhanced Conductive Molding Compound
Method and Apparatus for High Temperature Semiconductor Device Packages and Structures Using a Low Temperature Process
Wirebond Recess for Stacked Die
Method for Treating a Bond Pad of a Package Substrate
Method for Rf Management, Frequency Reuse and Increasing Overall System Capacity Using Network-Device-to-Network-Device Channel Estimation and Standard Beamforming Techniques
Sram with Embedded Rom
Patent:
8,995,178 →
Application:
14/069,192 →
Adaptive Erase Methods for Non-Volatile Memory
Sensor Die Grid Array Package
Application:
14/069,358 →
Publication:
US 2015/0115420
Sensor Protective Coating
Methods for Producing Near Zero Channel Length Field Drift Ldmos
Diodes with Multiple Junctions and Fabrication Methods Therefor
Efficient Apparatus and Method for Testing Digital Shadow Logic Around Non-Logic Design Structures
Trench Gate Transistor and Method of Fabricating Same
Application:
14/072,763 →
Publication:
US 2014/0159146
Mos Transistor with Forward Bulk-Biasing Circuit
Patent:
8,803,591 →
Application:
14/072,809 →
Method of Decoding a Received Sc-Fdma Symbol in a Receiver in a Ofdm Communication System, a Receiver, an Apparatus, an Ofdm Communication System and a Computer Program Product
Devices Having Automatically Adjustable Polarizers and Related Operating Methods
Monitoring System for Detecting Degradation of Integrated Circuit
Semiconductor Device and Method of Assembling Same
Binary Adder and Multiplier Circuit
Semiconductor Device with Integral Heat Sink
Static Modelling of an Electronic Device
Monitoring Coverage for Static Modelling of an Electronic Device
Wireless Power Transmitters with Wide Input Voltage Range and Methods of Their Operation
Semiconductor Devices with Integrated Schotky Diodes and Methods of Fabrication
Adjustable Power Splitters and Corresponding Methods & Apparatus
Methods of Making Semiconductor Devices with Low Leakage Schotky Contacts
Optically-Masked Microelectronic Packages and Methods for the Fabrication Thereof
Semiconductor Package with Gel Filled Cavity
Lead Frame with Power Bar for Semiconductor Device
Patent:
8,933,547 →
Application:
14/086,929 →
Pillar Bump Formed Using Spot-Laser
Multi-Die Sensor Device
Interrupt Driven Processing and Related Devices, Methods and Systems
Method and Apparatus for Network Streaming
Multi-Threaded System for Performing Atomic Binary Translations
Multiplexing and Demultiplexing Data
Packaged Semiconductor Devices and Methods of Their Fabrication
Mems Device Positioning Apparatus, Test System, and Test Method
Copper Ball Bond Interface Structure and Formation
Transistors with Field Plates Resistant to Field Plate Material Migration and Methods of Their Fabrication
Methods for the Production of Microelectronic Packages Having Radiofrequency Stand-Off Layers
Processing Data Flows Over a Single Common Public Radio Interface
Method and Apparatus for Resetting at Least One Node Within a Cpri Radio Base Station System
Application:
14/091,539 →
Publication:
US 2015/0146613
Method for Adding Leaf Node to Multi-Node Base Station
Bypass System and Method That Mimics Clock to Data Memory Read Timing
Processing System with Low Power Wake-Up Pad
Apparatus and a Method for Detecting Faults in the Delivery of Electrical Power to Electrical Loads
Amplifier with Adjustable Load
Method for Forming an Electrical Connection Between Metal Layers
Devices and Stacked Microelectronic Packages with Package Surface Conductors and Methods of Their Fabrication
Devices and Stacked Microelectronic Packages with Package Surface Conductors and Adjacent Trenches and Methods of Their Fabrication
Zener Diode Devices and Related Fabrication Methods
Stacked Die Sensor Package
Semiconductor Die Package with Insulated Wires for Routing Power Signals
Application:
14/098,560 →
Publication:
US 2015/0162269
Pressure Sensor with Built-in Calibration Capability
Vent Hole Sealing in Multiple Die Sensor Device
Patent:
9,018,029 →
Application:
14/099,502 →
Capacitive Cell Load Estimation Using Electromigration Analysis
Patent:
8,843,873 →
Application:
14/100,005 →
Synchronous Clock Multiplexer
Patent:
8,975,921 →
Application:
14/100,035 →
Non-Volatile Memory (Nvm) with Variable Verify Operations
Memories Having a Built-in Self-Test (Bist) Feature
Die-To-Die Inductive Communication Devices and Methods
Configurable Test Equipment
Application:
14/104,602 →
Publication:
US 2015/0168482
Glass Frit Wafer Bond Protective Structure
Semiconductor Package Having an Isolation Wall to Reduce Electromagnetic Coupling
Ststem and Method for Controlling Bypass of a Voltage Regulator
Analog-To-Digital Converter with Clock Halting Circuit
Patent:
9,000,968 →
Application:
14/108,294 →
System and Method to Test a Semiconductor Power Switch
Application:
14/110,877 →
Publication:
US 2014/0035610
Method and Apparatus for Generating Resource Efficient Computer Program Code
Application:
14/111,571 →
Publication:
US 2014/0040858
Method, Computer Program Product, and Apparatus for Simulating Electromagnetic Immunity of an Electronic Device
Application:
14/111,572 →
Publication:
US 2014/0039864
System and Method for Clock Signal Generation
Antenna Device, Amplifier and Receiver Circuit, and Radar Circuit
Application:
14/111,821 →
Publication:
US 2014/0035780
Method and Device for Diagnosing a Reservoir Capacitor of a Vehicle Passenger Protection System, and Vehicle Safety System Incorporating Such Device
Integrated Circuit Device and Method of Enabling Thermal Regulation Within an Integrated Circuit Device
Voltage Regulating Circuit with Selectable Voltage References and Method Therefor
Integrated Circuit Device and Method for Self-Heating an Integrated Circuit Device
Application:
14/115,710 →
Publication:
US 2014/0077856
Integrated Circuit Device, Voltage Regulator Module and Method for Compensating a Voltage Signal
Circuit Arrangement, Lighting Apparatus and Method of Crosstalk-Compensated Current Sensing
Method and Device for Encoding and Decoding an Image
Application:
14/119,372 →
Publication:
US 2014/0086309
Integrated Circuit Device and Method for Controlling an Operating Mode of an on-Die Memory
Application:
14/122,523 →
Publication:
US 2014/0115358
Process for Preparing Ball-Type Desulfurizer with High Sulfur Capacity and Product Thereof
Integrated Circuit Device and Method of Implementing Power Gating Within an Integrated Circuit Device
Processing Apparatus and Method of Synchronizing a First Processing Unit and a Second Processing Unit
Integrated Circuit Device and Method of Performing Cut-Through Forwarding of Packet Data
Level Shifter Circuit
Ion Sensitive Field Effect Transistors with Protection Diodes and Methods of Their Fabrication
Methods for Forming Semiconductor Devices with Stepped Bond Pads
Thermoplastic Toughening Material and Related Method
Low Leakage Cmos Cell with Low Voltage Swing
Analog Mixed Signal Model Equivalence Checking
Non-Volatile Memory (Nvm) Cell
SYSTEM IN A PACKAGE (SiP)
Method and System for Avoiding New Flow Packet Flood from Data Plane to Control Plane of a Network Device
Magnetic Pre-Conditioning of Magnetic Sensors
Automatic Generation of via Definitions Based on Manufacturability
Patent:
9,009,644 →
Application:
14/136,057 →
Semiconductor Devices with Inner Via
Semiconductor Manufacturing Using Design Verification with Markers
Application:
14/137,530 →
Publication:
US 2015/0178438
Transmitter and Method for Reducing the Peak-to-Average Power Ratio of a Digitally Modulated Communication Signal
Patent:
9,008,223 →
Application:
14/140,123 →
Hybrid Synchronous/Asynchronous Counter
Emiconductor Device with Die Top Power Connections
Application:
14/141,465 →
Publication:
US 2015/0187728
Waveform Generator
Patent:
8,847,639 →
Application:
14/141,466 →
Configurable Flip-Flop Circuit
Semiconductor Wafer Dicing Blade
Application:
14/141,471 →
Publication:
US 2015/0183131
Timing Path Slack Monitoring System
Patent:
8,887,120 →
Application:
14/141,473 →
Lead Frame and Substrate Semiconductor Package
Apparatus Fabrication Using Localized Annealing
System and Method for Low Cost Patching of High Voltage Operation Memory Space
Methods and Apparatus for Dissipating Heat from a Die Assembly
Application:
14/144,911 →
Publication:
US 2015/0187675
Ic Package with Metal Interconnect Structure Implemented Between Metal Layers of Die and Interposer
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 1, 2013
From: DAWSON, CHAD S.; JONES, PETER T.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031322/0447 →
Assignment of Assignor's Interest
Oct 4, 2013
From: STAUDINGER, JOSEPH; EMBAR, RAMANUJAM SRINIDHI
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031352/0053 →
Assignment of Assignor's Interest
Oct 4, 2013
From: EDWARDS, WILLIAM E.; GARRARD, MIKE R.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031344/0696 →
Assignment of Assignor's Interest
Oct 4, 2013
From: PRIEL, MICHAEL; TZYTKIN, DOV; SOFER, SERGEY
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 031348/0585 →
Assignment of Assignor's Interest
Oct 4, 2013
From: EDWARDS, WILLIAM E.; GARRARD, MIKE R.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031344/0558 →
Assignment of Assignor's Interest
Oct 4, 2013
From: TRAN, THANG M.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031351/0340 →
Assignment of Assignor's Interest
Oct 7, 2013
From: LIN, XIN; BLOMBERG, DANIEL J.; ZUO, JIANG-KAI
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031355/0638 →
Assignment of Assignor's Interest
Oct 7, 2013
From: ZHANG, ZHIHONG; BLOMBERG, DANIEL J.; YANG, HONGNING; ZUO, JIANG-KAI
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031356/0469 →
Assignment of Assignor's Interest
Oct 8, 2013
From: TAMMA, RAJA V.; TRAYLOR, KEVIN B.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031361/0590 →
Assignment of Assignor's Interest
Oct 8, 2013
From: TAMMA, RAJA V.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031360/0987 →
Assignment of Assignor's Interest
Oct 8, 2013
From: YATER, JANE A.; HONG, CHEONG MIN; KANG, SUNG-TAEG; PERERA, ASANGA H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031365/0346 →
Assignment of Assignor's Interest
Oct 8, 2013
From: PHAM, TIM V.; SWANSON, DEREK S.; UEHLING, TRENT S.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031366/0762 →
Assignment of Assignor's Interest
Oct 10, 2013
From: CUNNINGHAM, JEFFREY C.; SCOULLER, ROSS S.; SYZDEK, RONALD J.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031383/0471 →
Assignment of Assignor's Interest
Oct 13, 2013
From: ROY, AMIT; TAYAL, VIJAY; VERMA, CHETAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031396/0268 →
Assignment of Assignor's Interest
Oct 14, 2013
From: LIU, LIANJUN; BATES, JAMES S.; CHOWDHURY, MAMUR; MONK, DAVID J.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031401/0253 →
Assignment of Assignor's Interest
Oct 15, 2013
From: ZHAN, ROUYING; GILL, CHAI EAN; HONG, CHANGSOO; KANESHIRO, MICHAEL H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031404/0205 →
Assignment of Assignor's Interest
Oct 15, 2013
From: KAHNE, BRIAN C.; ARENDS, JOHN H.; COLLINS, RICHARD G.; HOLT, JAMES C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031410/0103 →
Assignment of Assignor's Interest
Oct 31, 2013
From: DEY, SANJOY K.; JAIN, MAYANK
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031515/0094 →
Supplement to Ip Security Agreement
Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0493 →
Supplement to Ip Security Agreement
Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., COLLATERAL AGENT
Reel/Frame 032445/0689 →
Supplement to Ip Security Agreement
Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0577 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0790 →
Assignment and Assumption of Security Interest in Patents
Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0420 →
Assignment and Assumption of Security Interest in Patents
Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0399 →
Corrective Assignment to Correct the Assignee Name Previously Recorded on Reel 037458 Frame 0399. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0390 →