INTEGRATED CIRCUIT DEVICE AND METHOD FOR CONTROLLING AN OPERATING MODE OF AN ON-DIE MEMORY
An integrated circuit device comprising at least one instruction processing module, at least one memory comprising at least one memory bank configurable to operate in a first functional mode and at least one further, lower-power mode, and at least one memory mode control module arranged to control switching of the at least one memory bank between the first functional mode and the at least one further, lower-power modes.
1 . An integrated circuit device comprising:
at least one instruction processing module;
at least one memory comprising at least one memory bank configurable to operate in a first functional mode and at least one further lower-power mode; and
at least one memory mode control module arranged to control switching of the at least one memory bank between the first functional mode and the at least one further lower-power mode, wherein
the memory mode control module is further arranged to receive at least one forward indication of at least one access to be made to the at least one memory bank of the at least one memory, and upon receipt of a forward indication of an access to be made to the at least one memory bank, to:
cause an increase in a clock cycle duration for at least a clock signal provided to the at least one instruction processing module, and
cause a change of mode of the at least one memory bank of the memory from the at least one further lower-power mode to the first functional mode.
2 . The integrated circuit device of claim 1 further comprising at least one decoding module arranged to decode at least one memory access instruction to be executed within the at least one instruction processing module.
3 . The integrated circuit device of claim 2 wherein the at least one memory mode control module is arranged to receive the at least one forward indications of the at least one access to be made to the at least one memory bank of the memory from the at least one decoding module.
4 . The integrated circuit device of claim 3 wherein the at least one decoding module is arranged to provide the at least one forward indication to the at least one memory bank of the at least one memory upon decoding a memory access instruction to be executed within the at least one instruction processing module.
5 . The integrated circuit device of claim 4 wherein the at least one decoding module is arranged to, upon decoding the at least one memory access instruction:
determine whether a switch of the at least one memory bank is required; and if the decoding module determines that a memory bank switch is required provide the forward indication of an access to be made to the at least one memory bank of the memory.
6 . The integrated circuit device of claim 1 wherein the at least one memory mode control module is arranged to, upon receipt of a forward indication of an access to be made to the at least one memory bank:
determine whether a memory bank switch is required for the memory bank access to which the forward indication relates; and if the at least one memory mode control module determines that a memory bank switch is required:
cause an increase in a clock cycle duration for at least the clock signal provided to the at least one instruction processing module; and
cause a change of mode of the at least one memory bank of the at least one memory to the first functional mode.
7 . The integrated circuit device of claim 1 wherein the at least one memory mode control module is arranged to control switching of the at least one memory bank between the first functional mode and the at least one further lower-power mode by configuring at least one voltage supply or reference voltage for the at least one memory bank.
8 . The integrated circuit device of claim 4 wherein the at least one memory mode control module is arranged to control switching of the at least one memory bank between the first and at least one further modes by configuring a virtual ground for the at least one memory bank.
9 . The integrated circuit device of claim 1 wherein the at least one memory mode control module is arranged to cause an increase in a clock cycle duration for at least one clock signal distributed throughout a plurality of components of the integrated circuit device that are synchronised with at least one from a group consisting of the instruction processing module, the memory block.
10 . The integrated circuit device of claim 1 wherein the at least one memory mode control module is further arranged to cause a reduction of the clock cycle duration for at least the clock signal to its previous clock cycle duration subsequent to the at least one memory bank entering the first functional mode.
11 . The integrated circuit device of claim 1 wherein the at least one further lower-power mode of the at least one memory bank of the at least one memory comprises a drowsy mode that allows bitcell content to be retained within the at least one memory bank.
12 . The integrated circuit device of claim 11 wherein the drowsy mode allows bitcell content to be retained within the at least one memory bank whilst reducing leakage current therefor.
13 . A method for controlling an operating mode of at least one memory bank of an on-die memory, the at least one memory bank being configurable to operate in a first functional mode and at least one further lower-power mode; the method comprising:
receiving at least one forward indication of at least one access to be made to the at least one memory bank of the on-die memory by at least one instruction processing module;
increasing a clock cycle duration for at least a clock signal provided to the at least one instruction processing module; and
causing the at least one memory bank to switch from the at least one lower-power mode to the first functional mode.
14 . The method of claim 13 further comprising:
decoding at least one memory access instruction to be executed within the at least one instruction processing module.
15 . The method of claim 14 further comprising:
decoding a memory access instruction to be executed within the at least one instruction processing module; and
providing the at least one forward indication of the at least one access to be made to the at least one memory bank of the on-die memory, upon said decoding the memory access instruction.
16 . The method of claim 15 further comprising, upon said decoding the memory access instruction:
determining whether a switch of the at least one memory bank of the on-die memory is required; and
if a switch of the at least one memory bank of the on-die memory is required, then providing the forward indication of an access to be made to the at least one memory bank of the memory.