SRAM with embedded ROM
View Patent ↗An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.
1. An integrated circuit, comprising:
a memory cell array including a first memory cell, the first memory cell includes:
first and second pass transistors that include a gate electrode connected to a word line;
a first inverter including:
a first pull-up transistor including a source electrode connected to a first voltage source and a body tie connected to a first well bias voltage, and
an output of the first inverter is coupled to a first complementary bit line via the first pass transistor; and
a second inverter including:
a first pull-up transistor including a source electrode connected to the first voltage source and a body tie connected to a second well bias voltage, the first well bias voltage is greater than the second well bias voltage when a Read-Only Memory (ROM) enable signal is set to a first state, and
an output of the second inverter is coupled to a first true bit line via the second pass transistor.
2. The integrated circuit of claim 1 , further comprising:
a second memory cell in the memory array, the second memory cell includes:
first and second pass transistors that include a gate electrode connected to the word line,
a first inverter including
a first pull-up transistor including a source electrode connected to the first voltage source and a body tie connected to the first well bias voltage, and
an output of the first inverter is coupled to a second true bit line via the first pass transistor,
a second inverter including
a second pull-up transistor including a source electrode connected to the first voltage source and a body tie connected to the second well bias voltage, and
an output of the second inverter is coupled to a second complementary bit line via the second pass transistor.
3. The integrated circuit of claim 1 , further comprising a memory controller configured to provide the ROM enable signal to the memory array.
4. The integrated circuit of claim 1 , wherein when the ROM enable signal is in a second state, the second well bias voltage is equal to the first well bias voltage and the first and second memory cells operate in a Static Random Access Memory (SRAM) mode.
5. The integrated circuit of claim 1 , further comprising:
a processor coupled to the memory module.
6. The integrated circuit of claim 5 , further comprising:
a body tie of the first and second pass transistors is coupled to a ground voltage.
7. The integrated circuit of claim 1 , the first memory cell further comprising:
a pull-down transistor coupled to the pull-up transistor in the first and second inverters, a body tie of the pull-down transistor is coupled to a first ground and a source electrode of the pull-down transistor is coupled to a second ground.
8. The integrated circuit of claim 1 , the second memory cell further comprising:
a pull-down transistor coupled to the pull-up transistor in the first and second inverters, a body tie of the pull-down transistor is coupled to a first ground and a source electrode of the pull-down transistor is coupled to a second ground.
9. The integrated circuit of claim 2 , further comprising:
the first memory cell outputs a logic HIGH when the ROM enable signal is in the first state; and
the second memory cell outputs a logic LOW when the ROM enable signal is in the first state.
10. An integrated circuit, comprising:
a first memory cell including a first pull-up transistor having a body tie coupled to a first well bias voltage and a drain electrode coupled to a first true bit line, and a second pull-up transistor having a body tie coupled to a second well bias voltage and a drain electrode coupled to a first complementary bit line;
a second memory cell including a first pull-up transistor having a body tie coupled to the second well bias voltage, a second pull-up transistor with a body tie coupled to the first well bias voltage, a drain electrode of the first pull-up transistor is coupled to a second true bit line and a drain electrode of the second pull-up transistor is coupled to a second complementary bit line;
the first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode; and
the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.
11. The integrated circuit of claim 10 , further comprising:
a memory controller configured to provide a ROM enable signal that is set to a first state to enable the ROM mode and disable the SRAM mode, and to a second state to enable the SRAM mode and disable the ROM mode.
12. The integrated circuit of claim 10 , the first memory cell further comprising:
a first pull-down transistor having a drain electrode coupled to the drain electrode of the first pull-up transistor, a source electrode of the first pull-down transistor is coupled to a first ground voltage supply and a body tie of the first pull-down transistor is coupled to a second ground voltage supply; and
a second pull-down transistor having a drain electrode coupled to the drain electrode of the second pull-up transistor, a drain electrode of the second pull-down transistor is coupled to a first ground voltage supply and a body tie of the second pull-down transistor is coupled to a second ground voltage supply.
13. The integrated circuit of claim 10 , the second memory cell further comprising:
a first pull-down transistor having a drain electrode coupled to the drain electrode of the first pull-up transistor, a source electrode of the first pull-down transistor is coupled to a first ground voltage supply and a body tie of the first pull-down transistor is coupled to a second ground voltage supply; and
a second pull-down transistor having a drain electrode coupled to the drain electrode of the second pull-up transistor, a source electrode of the second pull-down transistor is coupled to a first ground voltage supply and a body tie of the second pull-down transistor is coupled to a second ground voltage supply.
14. The integrated circuit of claim 10 , further comprising:
a source electrode of the first and second pull-up transistors of the first memory cell are coupled to a supply voltage;
a source electrode of the first and second pull-up transistors of the second memory cell are coupled to the supply voltage; and
the second well bias voltage is equal to the supply voltage during the ROM mode.
15. The integrated circuit of claim 10 , further comprising:
the first memory cell outputs a logic HIGH during the ROM mode; and
the second memory cell outputs a logic LOW during the ROM mode.
16. The integrated circuit of claim 10 , further comprising:
the first ground voltage supply and the second ground voltage supply are at different voltage levels during a low power mode.
17. The integrated circuit of claim 10 , further comprising:
in the first memory cell, a first pass transistor is connected between the drain electrode of the first pull-up transistor and a first true bit line and a second pass transistor is connected between the drain electrode of the second pull-up transistor and a first complementary bit line, a gate electrode of the first and second pass transistors is coupled to a word line; and
in the second memory cell, a first pass transistor is connected between the drain electrode of the first pull-up transistor and a second true bit line and a second pass transistor is connected between the drain electrode of the second pull-up transistor and a second complementary bit line, a gate electrode of the first and second pass transistors is coupled to the word line.
18. A method comprising:
forming a first memory cell in an integrated circuit, the first memory cell including a first pull-up transistor having a body tie coupled to a first well bias voltage, a second pull-up transistor with a body tie coupled to a second well bias voltage, a first pass transistor including a gate electrode coupled to a word line, a second pass transistor including a gate electrode coupled to the word line, a drain electrode of the first pull-up transistor is coupled to a first true bit line and a drain electrode of the second pull-up transistor is coupled to a first complementary bit line;
forming a second memory cell in the integrated circuit, the second memory cell including a first pull-up transistor having a body tie coupled to the second well bias voltage, a second pull-up transistor with a body tie coupled to the first well bias voltage, a first pass transistor including a gate electrode coupled to the word line, a second pass transistor including a gate electrode coupled to the word line, a drain electrode of the first pull-up transistor is coupled to a second true bit line and a drain electrode of the second pull-up transistor is coupled to a second complementary bit line;
forming a memory controller coupled to the first and second memory cells in the integrated circuit, the memory controller is operable to control the first well bias voltage to be lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and to control the first well bias voltage to be the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.
19. The method of claim 18 , further comprising:
forming a source electrode of the first and second pull-up transistors of the first memory cell coupled to a supply voltage (VDD);
forming a source electrode of the first and second pull-up transistors of the second memory cell coupled to the supply voltage; and
the memory controller is further operable to control the second well bias voltage to be equal to the supply voltage during the ROM mode.
20. The method of claim 18 , further comprising:
arranging the first and second memory cells to be part of programmed logic to be used during the ROM mode.