Transistors with field plates resistant to field plate material migration and methods of their fabrication
View Patent ↗An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials.
1. A transistor comprising:
a semiconductor substrate;
spaced-apart source and drain electrodes coupled to the semiconductor substrate;
a gate electrode coupled to the semiconductor substrate between the source and drain electrodes;
a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate; and
a field plate structure over the dielectric layer, wherein the field plate structure comprises multiple layers of a gold-containing material and one or more layers of indium interleaved with the multiple layers of the gold-containing material.
2. The transistor of claim 1 , wherein the field plate structure includes the gold-containing material in a range of 60 to 95 percent by volume, and includes the indium in a range of 5 to 40 percent by volume.
3. The transistor of claim 1 , wherein the field plate structure at least partially overlaps the gate electrode.
4. The transistor of claim 1 , wherein the field plate structure is adjacent to but does not overlap the gate electrode.
5. The transistor of claim 1 , wherein the semiconductor substrate is gallium nitride based.
6. A transistor comprising:
a gallium nitride based semiconductor substrate;
spaced-apart source and drain electrodes coupled to the semiconductor substrate;
a gate electrode coupled to the semiconductor substrate between the source and drain electrodes;
a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate; and
a field plate structure over the dielectric layer, wherein the field plate structure comprises multiple layers of a gold-containing material and one or more layers of indium interleaved with the multiple layers of the gold-containing material.
7. The transistor of claim 6 , wherein the field plate structure includes the gold-containing material in a range of 60 to 95 percent by volume, and includes the indium in a range of 5 to 40 percent by volume.
8. A method of fabricating a transistor, the method comprising the steps of:
forming a gate electrode over a semiconductor substrate;
forming a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate; and
forming a field plate structure over the dielectric layer, wherein forming the field plate structure comprises forming a stack of layers by
depositing, by evaporation, a first indium layer,
depositing a first gold-containing material layer over the first indium layer,
depositing, by evaporation, a second indium layer over the first gold-containing material layer, and
depositing a second gold-containing material layer over the second indium layer.
9. The method of claim 8 , wherein forming the field plate structure further comprises:
heating the stack of layers to a temperature that causes the first and second gold-containing material layers and the first and second indium layers to partially combined together.
10. The method of claim 8 , further comprising:
forming spaced-apart source and drain electrodes coupled to the semiconductor substrate on either side of the gate electrode.
11. A transistor comprising:
a semiconductor substrate;
spaced-apart source and drain electrodes coupled to the semiconductor substrate;
a gate electrode coupled to the semiconductor substrate between the source and drain electrodes;
a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate; and
a field plate structure over the dielectric layer, wherein the field plate structure comprises multiple layers of a gold-containing material and multiple layers of indium, wherein the multiple layers of the gold-containing material are interleaved with the multiple layers of indium.