System for placing dummy tiles in metal layers of integrated circuit design
View Patent ↗An electronic design automation (EDA) tool for inserting dummy tiles between interconnect lines of an integrated circuit design includes a memory for storing the integrated circuit design and a processor in communication with the memory. The processor identifies those interconnect lines that are at different voltage levels, have a length greater than a predefined threshold length and a spacing less than a predefined threshold spacing, and inserts blockage areas between such interconnect lines. The processor skips the blockage areas and adds dummy tiles only between those interconnect lines that do not meet predetermined criteria.
1. An electronic design automation (EDA) tool for inserting dummy tiles in a metal layer of an integrated circuit design, wherein the metal layer includes a plurality of interconnect lines, the EDA tool comprising:
a memory that stores the integrated circuit design and includes a routing database including routing information of the plurality of interconnect lines; and
a processor in communication with the memory, wherein the processor includes:
means for identifying a first set of interconnect lines of the plurality of interconnect lines that are at different voltage levels, using the routing information;
means for defining a blockage between first and second interconnect lines of the first set of interconnect lines, based on at least a length of the first and second interconnect lines being greater than a first predefined threshold and a spacing between the first and second interconnect lines being less than a second predefined threshold;
means for inserting the dummy tiles between the plurality of interconnect lines excluding the first and second interconnect lines;
means for removing the blockage between the first and second interconnect lines after the insertion of the dummy tiles is complete; and
means for checking a density of the plurality of interconnect lines after the insertion of the dummy lines is complete.
2. The EDA tool of claim 1 , wherein a blockage is defined when a length of each of the first and second interconnect lines is greater than a first predefined threshold.
3. The EDA tool of claim 1 , wherein a blockage is defined when a spacing between the first and second interconnect lines is less than a second predefined threshold.
4. The EDA tool of claim 1 , wherein the density of the plurality of interconnect lines is less than a predefined density criteria.
5. The EDA tool of claim 4 , wherein the routing information includes at least one of interconnect routing design and layout patterns of the integrated circuit design, the predefined density criteria, a length and thickness of each interconnect line, a spacing and capacitance between the plurality of interconnect lines, a voltage level of each interconnect line, and first second predefined thresholds.
6. An electronic design automation (EDA) tool for inserting dummy tiles in a metal layer of an integrated circuit design, wherein the metal layer includes a plurality of interconnect lines, the EDA tool comprising:
a memory that stores the integrated circuit design and includes a routing database, wherein the routing database includes routing information of the plurality of interconnect lines; and
a processor in communication with the memory, wherein the processor:
identifies a first set of interconnect lines of the plurality of interconnect lines based on the routing information, wherein the first set of interconnect lines are at different voltage levels;
defines a blockage between first and second interconnect lines of the first set of interconnect lines, based on at least a length of the first and second interconnect lines being greater than a first predefined threshold and a spacing between the first and second interconnect lines being less than a second predefined threshold;
inserts the dummy tiles between the plurality of interconnect lines by excluding the first and second interconnect lines;
removes the blockage between the first and second interconnect lines after the insertion of the dummy tiles is complete; and
checks a density of the plurality of interconnect lines after the insertion of the dummy lines is complete.
7. The EDA tool of claim 6 , wherein the density of the plurality of interconnect lines is less than a predefined density criteria.
8. The EDA tool of claim 7 , wherein the routing information includes at least one of interconnect routing design and layout patterns of the integrated circuit design, the predefined density criteria, a length and thickness of each interconnect line, a spacing and capacitance between the plurality of interconnect lines, a voltage level of each interconnect line, and first second predefined thresholds.
9. The EDA tool of claim 6 , wherein the processor further modifies the first and second predefined thresholds.
10. A method for inserting dummy tiles in a metal layer of an integrated circuit design using an electronic design automation (EDA) tool, wherein the metal layer includes a plurality of interconnect lines, and wherein the EDA tool includes a processor and a memory in communication with the processor and wherein the memory stores the integrated circuit design and includes a routing database, and wherein the routing database includes routing information of the plurality of interconnect lines, the method comprising:
identifying a first set of interconnect lines of the plurality of interconnect lines based on the routing information, wherein the first set of interconnect lines are at different voltage levels;
defining a blockage between first and second interconnect lines of the first set of interconnect lines based on at least a length of the first and second interconnect lines being greater than a first predefined threshold and a spacing between the first and second interconnect lines being less than a second predefined threshold;
inserting the dummy tiles between the plurality of interconnect lines by excluding the blockage areas between the first and second interconnect lines;
removing the blockage between the first and second interconnect lines, after the insertion of the dummy tiles is complete, using the processor; and
checking a density of the plurality of interconnect lines after the insertion of the dummy lines is complete using the processor.
11. The method of claim 10 , wherein the blockage is defined when a length of each of the first and second interconnect lines is greater than a first predefined threshold.
12. The method of claim 10 , wherein the blockage is defined when a spacing between the first and second interconnect lines is less than a second predefined threshold.
13. The method of claim 10 , wherein the density of the plurality of interconnect lines is less than a predefined density criteria.
14. The method of claim 13 , wherein the routing information includes at least one of interconnect routing design and layout patterns of the integrated circuit design, the predefined density criteria, a length and thickness of each interconnect line, a spacing and capacitance between the plurality of interconnect lines, a voltage level of each interconnect line, and first second predefined thresholds.