System and method for low cost patching of high voltage operation memory space
View Patent ↗A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching is provided for just a small area of the possible flash memory map, and program flow is controlled by presenting the CPU core's own address to redirect the program counter to the patch area.
1. A system comprising:
a processor configured to request a memory address, wherein the memory address comprises firmware executable by the processor;
memory access circuitry, external to the processor, and coupled to the processor, and configured to
determine whether the requested memory address corresponds to an address of a patch for the requested memory address, and
load a program counter of the processor with the address of the patch in place of instructions at the requested memory address;
a flash memory configured to store a first subset of the firmware; and
a register memory separate from the flash memory and configured to store a second subset of the firmware, wherein
the requested memory address is stored in the register memory, and
the register memory is configured for access only when the flash memory is unavailable for read access, wherein the flash memory and the register memory are configured to provide data corresponding to the requested memory address to the processor in response to the request for the memory address.
2. The system of claim 1 wherein the memory access circuitry comprises:
comparator circuitry configured to compare the requested memory address with a patch address location address;
patch selector circuitry configured to provide a patch redirect register address in response to the memory address matching the patch address location address, wherein
the patch redirect register address provides the address of the patch for the requested memory address.
3. The system of claim 2 further comprising a register memory wherein the register memory comprises the patch redirect register and the address of the patch for the requested memory address.
4. The system of claim 3 wherein the register memory further comprises one or more boot memory registers.
5. The system of claim 2 wherein the memory access circuitry further comprises:
loader circuitry configured to provide the address of the patch for the requested memory address to the processor.
6. The system of claim 1 wherein the second subset of the firmware is configured for access by the processor during a period when the flash memory is operating in a non-executable mode comprising one of program or erase mode.
7. The system of claim 1 wherein the second subset of the firmware is configured for access by the processor during a period when the flash memory is operating in a high voltage mode.
8. A system on a chip, the system comprising:
a processor configured to request a memory address;
a memory, coupled to the processor, and configured to
store firmware executable by the processor, wherein the memory comprises
a flash memory configured to store a first subset of the firmware,
a register memory configured to store a second subset of the firmware, and
the second subset of the firmware comprising the requested memory address and a patch for the requested memory address; and
memory access circuitry, coupled to the memory and the processor, and configured to provide a program counter of the processor with the address of the patch in place of instructions at the requested memory address, in response to the request for the memory address, wherein
the register memory is configured for access only when the flash memory is unavailable for read access, and
the flash memory and the register memory are configured to provide data corresponding to the requested memory address to the processor in response to the request for the memory address.
9. The system of claim 8 wherein the memory access circuitry comprises:
a comparator configured to compare the requested memory address with a patch address location address; and
a patch selector configured to provide a patch redirect register address in response to the memory address matching the patch address location address, wherein the patch redirect register address provides the address of the patch for the requested memory address.
10. The system of claim 9 further comprising a register memory configured to store the patch redirect register and the address of the patch for the requested memory address.
11. The system of claim 8 wherein the memory access circuitry further comprises loader circuitry configured to provide the address of the patch for the requested memory address to the processor.