Static modelling of an electronic device
View Patent ↗A design verification system verifies an electronic device design based on a static model of the electronic device. The static model is an expression of the relationships between modules of the electronic device design and relationships between the behaviors of those modules that can be expressed as set of logical relationships. The static model does not rely on a time variable, but instead reflects a fixed set of relationships between the electronic device modules and between behaviors of the electronic device modules. The static model can be employed by a solver, that identifies whether or how the mathematical relationships of the static model can be reconciled, given a set of constraints. The solver results can be analyzed to identify whether there are errors in the device design, such as resource conflicts, failure of the design to achieve a desired configuration, and the like.
1. A computer-implemented method comprising:
generating a static model comprising a set of logical equations reflecting one or more potential configurations of elements of a design for a processor, integrated circuit, or system-on-a-chip based on a data file describing the elements of the design for the processor, integrated circuit, or system-on-a-chip and fixed relationships between the elements and between behaviors of the elements that remain unchanged over time;
solving the static model to generate a first solution to verify one or more potential configurations of the elements of the processor, integrated circuit, or system-on-a-chip based on the design, wherein solving the static model comprises identifying whether the logical equations comprising the static model can be resolved so that there are no logical inconsistencies in the logical equations based on a set of constraint data for the one or more potential configurations;
modifying the design based on a plurality of solutions of the static model, the plurality of solutions including the first solution;
storing the modified design at a computer system; and
forming a processor, integrated circuit, or system-on-a-chip based on the modified design, wherein forming comprises manufacturing, fabricating or assembling.
2. The method of claim 1 , wherein generating the static model comprises:
generating a set of node variables based on the data file, each node variable in the set of node variables corresponding to an element of the design.
3. The method of claim 1 , wherein generating the static model comprises:
generating arc variables to indicate relationships between node variables.
4. The method of claim 3 , wherein the static model comprises:
a set of logical relationships between a parent node of the node variables, P child nodes of the parent node, and a set of arc variables associated with the parent node and the P child nodes, the set of logical relationships indicating that if the parent node is in a true state, at least M of the P child nodes and no more than N of the P child nodes are implied to also be in a true state, wherein M, N, and P are each integer values.
5. The method of claim 4 , wherein M and N have the same value.
6. The method of claim 4 , wherein M and N are equal to P.
7. The method of claim 4 , wherein M is 0 and N is equal to P.
8. The method of claim 3 wherein the static model comprises:
a set of logical relationships between P parent nodes of the node variables and a child node of the P parent nodes, the set of logical relationships indicating that if the child node is in a true state, no more than R of the P parent nodes are implied to also be in a true state, wherein P and R are each integer values.
9. The method of claim 1 , further comprising:
in response to solving the static model, generating coverage data indicating logical value assigned to node variables and arc variables of the static model for solving the static model.
10. The method of claim 1 , wherein the set of constraint data comprises user-defined constraint information indicating node variables and arc variables of the static model that are to be set to a true state for solving the static model.
11. A method, comprising:
receiving a static model comprising a set of logical equations reflecting one or more potential configurations of elements of a design for a processor, integrated circuit, or system-on-a-chip and indicating static behavioral relationships between elements of a design for a processor, integrated circuit, or system-on-a-chip that remain unchanged over time;
solving the static model to generate a first solution to verify specified predicted behavior for one or more potential configurations of elements of the processor, integrated circuit, or system-on-a-chip based on the design, wherein solving the static model comprises identifying whether the logical equations comprising the static model can be resolved so that there are no logical inconsistencies in the logical equations based on a set of constraint data for the one or more potential configurations;
modifying the design based on the first solution;
storing the modified design at a computer system; and
forming a processor, integrated circuit, or system-on-a-chip based on the modified design, wherein forming comprises manufacturing, fabricating or assembling.
12. The method of claim 11 , the constraint data indicates that one or more elements of the design are required; and
solving the static model based on the constraint data.
13. The method of claim 12 , wherein the constraint data indicates that an element of the design is prohibited.
14. The method of claim 11 , wherein the static model includes:
nodes stored in a data structure to indicate relationships between the nodes, the relationships between the nodes indicative of predicted relationships between corresponding elements of the design.
15. A non-transitory computer-readable storage medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
generate a static model comprising a set of logical equations reflecting one or more potential configurations of elements of a design for a processor, integrated circuit, or system-on-a-chip based on a data file describing elements of the design for the processor, integrated circuit, or system-on-a-chip and static behavioral relationships between the elements that remain unchanged over time;
solve the static model to generate a first solution to verify one or more potential configurations of the processor, integrated circuit, or system-on-a-chip based on the design, wherein solving the static model comprises identifying whether the logical equations comprising the static model can be resolved so that there are no logical inconsistencies in the logical equations based on a set of constraint data for the one or more potential configurations;
modify the design based on the first solution;
store the modified design at a computer system; and
manufacture, fabricate, or assemble a processor, integrated circuit, or system-on-a-chip based on the modified design.
16. The computer readable medium of claim 15 , wherein the instructions to generate the static model comprise instructions to manipulate at least one processor to:
generate a set of node variables based on the data file, each node variable in the set of node variables corresponding to an element of the design.
17. The computer readable medium of claim 15 , wherein the instructions to generate the static model comprise instructions to manipulate at least one processor to:
generate arc variables to indicate relationships between node variables that are dependent on a common node.
18. The computer readable medium of claim 17 , wherein the static model comprises:
a set of logical relationships between a parent node of the node variables, P child nodes of the parent node, and a set of arc variables associated with the parent node and the P child nodes, the set of logical relationships indicating that if the parent node is in a true state, at least M of the P child nodes and no more than N of the P child nodes are implied to also be in a true state, wherein M, N, and P are each integer values.
19. The computer readable medium of claim 15 , further comprising instructions to manipulate at least one processor to:
generate coverage data indicating logical value assigned to node variables and arc variables of the static model for solving the static model.
20. The computer readable medium of claim 15 , wherein the set of constraint data indicates node variables and arc variables of the static model that are to be set to a true state for solving the static model.