Granted Patent B2

US 9,111,870 · App. 14/056,844 · Granted Aug 18, 2015

Abstract

Claims (55)

1. A method for fabricating a microelectronic package, comprising:

encapsulating a device stack within a molded panel having a frontside and a backside, the device stack comprising:

an upper semiconductor die;

an interconnect buffer layer formed over the upper semiconductor die and covered by the frontside of the molded panel; and

an inner molded body surrounding the upper semiconductor die and underlying the interconnect buffer layer;

removing material from the frontside the molded panel to expose the interconnect buffer layer therethrough;

producing one or more frontside redistribution layers over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer; and

singulating the molded panel to yield a microelectronic package including a molded package body containing the device stack and surrounding the inner molded body and the interconnect buffer layer.

2. The method of claim 1 wherein the device stack further comprises a lower semiconductor die positioned in a back-to-back relationship with the upper semiconductor die.

3. The method of claim 2 wherein the device stack further comprises a die attach layer bonding the backside of the upper semiconductor die to the backside of the lower semiconductor die.

4. The method of claim 3 wherein the upper semiconductor die is electrically coupled to the lower semiconductor die through the die attach layer.

5. The method of claim 1 , further comprising:

encapsulating the upper semiconductor die within an initial molded panel;

forming the interconnect buffer layer over the initial molded panel;

singulating the initial molded panel to yield an upper package layer including the inner molded body, the upper semiconductor die surrounded by the inner molded body, and the interconnect buffer layer overlying the inner molded body and the upper semiconductor die; and

positioning the upper package layer over at least one lower microelectronic device to produce the device stack.

6. The method of claim 5 further comprising planarizing the backside of the initial molded panel to reveal the backside of the upper semiconductor die therethrough prior to forming the interconnect buffer layer.

7. The method of claim 1 wherein the upper semiconductor die comprises a frontside on which a plurality of bond pads is located, and wherein the interconnect buffer layer comprises:

a dielectric film formed over the frontside of the semiconductor die; and

a plurality of contacts extending through the dielectric film and in ohmic contact with the plurality of bond pads.

8. The method of claim 7 wherein the plurality of contacts comprises a plurality of plated pillars.

9. The method of claim 1 wherein removing material from the frontside the molded panel comprises planarizing the frontside of the molded panel to remove a predetermined thickness from the molded panel and impart the molded panel with a substantially planar frontside surface.

10. The method of claim 9 wherein a predetermined thickness is also removed form the interconnect buffer layer during planarization of the frontside of the molded panel.

11. The method of claim 1 wherein the device stack further comprises a lower microelectronic device, and wherein the method further comprises producing one or more backside redistribution layers over the backside of the molded panel and electrically coupled to the lower microelectronic device.

12. The method of claim 11 further comprising:

forming at least one through package via through the molded panel after encapsulating the device stack therein; and

producing a backside contact array over the backside redistribution layers prior to singulation of the molded panel;

wherein the upper semiconductor die is electrically coupled to at least one of the lower microelectronic device and the backside contact array through the frontside redistribution layers, the through package via, and the backside redistributions layers.

13. The method of claim 1 wherein the inner molded body is produced prior to the outer molded body during an initial panelization and singulation process utilized to initially encapsulate the upper semiconductor die.

14. A method for fabricating a microelectronic package, comprising:

bonding an upper package layer to a lower microelectronic device to produce a device stack, the upper package layer comprising:

an inner molded body;

at least one upper microelectronic device surrounded by the inner molded body; and

an interconnect buffer layer formed over the inner molded body and over the at least one upper microelectronic device;

encapsulating the device stack within a molded panel having a frontside and a backside through which the lower microelectronic device is exposed;

planarizing the frontside of the molded panel to reveal the interconnect buffer layer therethrough;

producing one or more frontside redistribution layers over the frontside of the molded panel and electrically coupled to the at least one upper microelectronic device through the interconnect buffer layer; and

singulating the molded panel to yield a microelectronic package including an outer molded package body containing the device stack and formed around the inner molded body and the interconnect buffer layer.

15. The method of claim 14 wherein the at least one upper microelectronic device comprises:

a first upper microelectronic device encapsulated within the inner molded body; and

a second upper microelectronic device encapsulated within the inner molded body adjacent the first upper microelectronic device.

16. The method of claim 15 wherein the upper package layer further comprises a buried interconnect layer formed over the inner molded body opposite the interconnect buffer layer, the first and second upper microelectronic devices electrically coupled through the buried interconnect buffer layer.

17. The method of claim 15 wherein first and second upper microelectronic device comprise first and second semiconductor die, respectively, and wherein the buried interconnect buffer layer electrically couples an electrically-conductive feature on the backside of the first semiconductor die to an electrically-conductive feature on the backside of the second semiconductor die.

18. The method of claim 14 wherein the inner molded body is produced utilizing a first overmolding process, wherein the molded panel is produced utilizing a second overmolding process performed subsequent to the first overmolding process, and wherein the inner molded body comprises a singulated piece of a molded panel produced pursuant to the first overmolding process.

19. A microelectronic package, comprising:

a device stack, comprising:

a lower microelectronic device;

a first upper microelectronic device positioned over the lower microelectronic device;

an inner molded body surrounding the first upper microelectronic device;

an interconnect buffer layer disposed over the first upper microelectronic device and the inner molded body;

an outer molded body in which the device stack is embedded, the outer molded body formed around the inner molded body and the interconnect buffer layer;

one or more frontside redistribution layers disposed over a frontside of the outer molded body and electrically coupled to the first upper microelectronic device through the interconnect buffer layer;

one or more backside redistribution layers disposed over a backside of the outer molded body and electrically coupled to the lower microelectronic device; and

at least one contact array electrically coupled to the lower microelectronic device through the backside redistribution layers and to the upper microelectronic device through the frontside redistribution layers and the interconnect buffer layer.

20. The microelectronic package of claim 19 wherein the device stack further comprises a second upper microelectronic device embedded within the inner molded body adjacent the first microelectronic device.

Assignments (22)