Memories having a built-in self-test (BIST) feature
View Patent ↗A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.
1. A memory system, comprising:
a memory; and
a built-in self-test (BIST) unit coupled to the memory, wherein the BIST unit is configured to:
run a test pattern on the memory to accumulate a fault signature; and
store fault signature information based on the accumulated fault signature at multiple locations in the memory, wherein
a same copy of the fault signature information is stored at two or more of the multiple locations in the memory on which the test pattern is run.
2. The memory system of claim 1 , wherein the BIST unit is further configured to encode the accumulated fault signature in accordance with an error correcting algorithm to form the fault signature information.
3. The memory system of claim 1 , wherein the BIST unit is configured to store the fault signature information based on the accumulated fault signature by being further configured to store the accumulated fault signature at the multiple locations in the memory.
4. The memory system of claim 3 , wherein the multiple locations in the memory are an odd number of memory locations.
5. The memory system of claim 3 , where the multiple locations in the memory correspond to predetermined locations of the memory which are spaced apart from each other.
6. The memory system of claim 1 , wherein the BIST unit is configured to store the fault signature information based on the accumulated fault signature by being further configured to store the accumulated fault signature at ones of the multiple locations in the memory, and store an inverse of the accumulated fault signature at others of the multiple locations in the memory.
7. The memory system of claim 1 , wherein the memory system further comprises:
a second memory; and
a second BIST unit, coupled to the second memory, and configured to:
run a second test pattern on the second memory to accumulate a second fault signature; and
store second fault signature information based on the second accumulated fault signature at multiple locations in the second memory on which the second test pattern is run.
8. The memory system of claim 1 , where the multiple locations in the memory correspond to predetermined locations of the memory which are spaced apart from each other.
9. The memory system of claim 1 , wherein the memory system further comprises:
a second memory, wherein the BIST unit is coupled to the second memory and further configured to:
run a second test pattern on the second memory to accumulate a second fault signature; and
store second fault signature information based on the second accumulated fault signature at multiple locations in the second memory on which the second test pattern is run.
10. A memory system, comprising:
a memory; and
a BIST unit coupled to the memory, comprising:
a pattern generator configured to apply a test pattern to the memory;
a comparator configured to, in response to application of the test pattern, compare data read from the memory with expected data;
a fault accumulator configured to accumulate a fault signature for the memory based on comparisons performed by the comparator; and
control circuitry configured to store fault signature information based on the accumulated fault signature at multiple locations of in the memory, wherein
a same copy of the fault signature information is stored at two or more of the multiple locations in the memory on which the test pattern is run.
11. The memory system of claim 10 , further comprising:
a second memory, wherein:
the pattern generator of the BIST unit is further configured to apply a second test pattern to the second memory;
the comparator is further configured to, in response to application of the second test pattern, compare second read data from the second memory with second expected data;
the fault accumulator is further configured to accumulate a second fault signature for the second memory based on comparisons performed by the comparator; and
the control circuitry is further configured to store second fault signature information based on the accumulated second fault signature at multiple locations of in the second memory on which the second test pattern is run.
12. The memory system of claim 11 , wherein the fault accumulator includes a single register configured to store the accumulated fault signature during testing of the memory and the accumulated second signature during testing of the second memory.
13. The memory system of claim 10 , wherein the BIST unit is further configured to encode the accumulated fault signature in accordance with an error correcting algorithm to form the fault signature information.
14. The memory system of claim 10 , wherein the control circuitry is configured to store the fault signature information based on the accumulated fault signature by being further configured to store the accumulated fault signature at the multiple locations in the memory.
15. The memory system of claim 14 , wherein the multiple locations in the memory are an odd number of memory locations.
16. The memory system of claim 10 , wherein the control circuitry is configured to store the fault signature information based on the accumulated fault signature by being further configured to store the accumulated fault signature at ones of the multiple locations in the memory and store an inverse of the accumulated fault signature at others of the multiple locations in the memory.
17. A method comprising:
selecting a first memory for testing;
running a test pattern on the selected first memory to accumulate a fault signature for the memory; and
storing fault signature information based on the accumulated fault signature at multiple locations in the selected first memory, wherein
a same copy of the fault signature information is stored at two or more of the multiple locations in the selected first memory on which the test pattern is run.
18. The method of claim 17 , further comprising, prior to the storing the fault signature information, encoding the accumulated fault signature in accordance with an error correcting algorithm to form the fault signature information.
19. The method of claim 17 , wherein the storing the fault signature information based on the accumulated fault signature comprises storing the accumulated fault signature at the multiple locations in the selected first memory.
20. The method of claim 17 , further comprising:
retrieving the fault signature information from the multiple locations in the selected first memory; and
running an error correction algorithm on the retrieved fault signature information for the memory to generate an error corrected fault signature for the selected first memory.
21. The method of claim 20 , wherein the running the error correction algorithm comprises
comparing the fault signature information retrieved from each of the multiple locations to determine a final fault signature information, wherein
a majority of the fault signature information retrieved from each of the multiple locations indicates a same fault signature information, and
the final fault signature information comprises the same fault signature information.