IP Library Granted Patent US 9,978,689
Granted Patent B2
US 9,978,689 · App. 14/133,217 · Granted May 22, 2018

Ion sensitive field effect transistors with protection diodes and methods of their fabrication

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Quick Facts
Patent No.
US 9,978,689
App. No.
14/133,217
Granted
May 22, 2018
Kind
B2
Abstract

An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.

Claims (73)

1. An Ion Sensitive Field Effect Transistor (ISFET) structure comprising:

a substrate having a surface, wherein the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

a source region and a drain region formed within the substrate and spatially separated across the surface of the substrate by a channel region, wherein the source region and the drain region are regions of a second conductivity type formed within the first region;

a gate dielectric formed on the surface of the substrate over the channel region;

a gate formed on the gate dielectric;

multiple conductive structures overlying the surface of the substrate, wherein the multiple conductive structures include

a floating gate structure formed over the gate dielectric and including the gate, and

a sense plate structure electrically coupled to the floating gate structure and configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure; and

a first protection diode circuit coupled between one of the multiple conductive structures and the substrate, wherein the first protection diode circuit comprises

a first well region of the second conductivity type formed within the first region,

a second well region of the first conductivity type formed within the first well region,

a second region of the second conductivity type formed within the second well region,

at least one PN junction between the first and second well regions and the second region, including a first PN junction formed between the first region and the first well region, a second PN junction formed between the first well region and the second well region, and a third PN junction formed between the second well region and the second region, wherein the at least one PN junction correspond to first and second diodes of multiple series-coupled diodes, wherein a first type of terminal of the first diode of the multiple series-coupled diodes is coupled to the one of the multiple conductive structures, and a second type of terminal of the first diode is connected to the second type of terminal of the second diode of the multiple series-coupled diodes, and

a bias contact coupled to a terminal of the first or second diode, whereas the bias contact is configured to provide a bias voltage to the first protection diode circuit that alters a point at which a PN junction of the first protection diode circuit becomes forward biased to avoid discharging charges associated with the target ion or molecule through the first protection diode circuit.

2. The ISFET structure of claim 1 , wherein:

the first protection diode circuit is coupled to the floating gate structure, and

the ISFET structure further comprises:

a second protection diode circuit coupled to the sense plate structure, wherein the second protection diode circuit comprises at least one second PN junction between a second set of adjacent regions of opposite conductivity type formed within the substrate.

3. The ISFET structure of claim 1 , wherein the first protection diode circuit further comprises:

a third region of the first conductivity type formed within the second well region, and wherein the ISFET structure further comprises:

a contact coupled to the third region and configured to receive a voltage to bias the second well region.

4. The ISFET structure of claim 1 , wherein the sense plate structure comprises:

a conductive sense plate formed from a first metal layer proximate a surface of the ISFET structure;

a first metal conductor formed in a second metal layer underlying the first metal layer; and

at least one conductive via electrically coupling the first metal conductor and the sense plate.

5. The ISFET structure of claim 4 , wherein the floating gate structure comprises:

the gate formed on the gate dielectric;

a second metal conductor formed in a third metal layer underlying the second metal layer; and

at least one conductive via electrically coupling the second metal conductor and the gate.

6. The ISFET structure of claim 5 , further comprising:

an oxide layer formed between the first and second metal conductors, wherein the first and second metal conductors and the oxide layer function to capacitively couple the sense plate structure and the floating gate structure.

7. The ISFET structure of claim 5 , wherein the gate is a polysilicon gate.

8. The ISFET structure of claim 1 , further comprising:

at least one control gate structure electrically coupled to the floating gate structure, the control gate structure configured to accept a voltage bias and to cause the movement of charge between the floating gate structure and the control gate structure in response to the voltage bias.

9. The ISFET structure of claim 1 , wherein the first type of terminal is an anode and the second type of terminal is a cathode.

10. The ISFET structure of claim 1 , wherein the first type of terminal is a cathode and the second type of terminal is an anode.

11. An Ion Sensitive Field Effect Transistor (ISFET) structure comprising:

a substrate having a surface, wherein the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

a source region and a drain region formed within the substrate and spatially separated across the surface of the substrate by a channel region, wherein the source region and the drain region are regions of a second conductivity type formed within the first region;

a gate dielectric formed on the surface of the substrate over the channel region;

a gate formed on the gate dielectric;

a floating gate structure formed over the gate dielectric and including the gate;

a sense plate structure electrically coupled to the floating gate structure and configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure; and

a first protection diode circuit coupled between the floating gate structure and the substrate, wherein the first protection diode circuit comprises at least one PN junction between a first set of adjacent regions of opposite conductivity type formed within the substrate, and wherein the first protection diode circuit comprises

a first well region of the second conductivity type formed within the first region,

a second well region of the first conductivity type formed within the first well region,

a second region of the second conductivity type formed within the second well region, wherein the at least one PN junction includes a first PN junction formed between the first region and the first well region, a second PN junction formed between the first well region and the second well region, and a third PN junction formed between the second well region and the second region, wherein the at least one PN junction correspond to first and second diodes of multiple series-coupled diodes, wherein a first type of terminal of the first diode of the multiple series-coupled diodes is coupled to the floating gate structure, and a second type of terminal of the first diode is connected to a second type of terminal of the second diode of the multiple series-coupled diodes, and

a bias contact coupled to a terminal of the first or second diode, whereas the bias contact is configured to provide a bias voltage to the first protection diode circuit that alters a point at which a PN junction of the at least one PN junction becomes forward biased to avoid discharging charges associated with the target ion or molecule through the first protection diode circuit.

12. The ISFET structure of claim 11 , further comprising:

a second protection diode circuit coupled to the sense plate structure, wherein the second protection diode circuit comprises at least one second PN junction between a second set of adjacent regions of opposite conductivity type formed within the substrate.

13. The ISFET structure of claim 11 , wherein the first protection diode circuit further comprises:

a third region of the first conductivity type formed within the second well region, and wherein the ISFET structure further comprises:

a contact coupled to the third region and configured to receive a voltage to bias the second well region.

14. A method of fabricating an Ion Sensitive Field Effect Transistor (ISFET) structure, the method comprising the steps of:

forming a gate dielectric and a gate on a surface of a substrate over a channel region, wherein the substrate includes a first region of a first conductivity type that extends to the surface of the substrate;

forming a source region and a drain region of a second conductivity type within the first region, wherein the source region and the drain region are spatially separated across the surface of the substrate by the channel region;

forming a first protection diode circuit by

forming a first well region of the second conductivity type within the first region,

forming a second well region of the first conductivity type within the first well region, and

forming a second region of the second conductivity type within the second well region,

wherein the first and second well regions and the second region form at least one PN junction that includes a first PN junction formed between the first region and the first well region, a second PN junction formed between the first well region and the second well region, and a third PN junction formed between the second well region and the second region, wherein the at least one PN junction correspond to first and second diodes of multiple protection diodes, wherein each of the multiple protection diodes has a first type of terminal and a second type of terminal, and the second type of terminal of the first diode of the multiple protection diodes is connected to the second type of terminal of the second diode of the multiple protection diodes;

forming multiple conductive structures overlying the surface of the substrate, wherein the multiple conductive structures include

a floating gate structure coupled to and including the gate, and

a sense plate structure electrically coupled to the floating gate structure and configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure;

electrically coupling the first type of terminal of the first diode of the multiple protection diodes to one of the multiple conductive structures; and

electrically coupling a contact to the second type of terminal of the first diode, wherein the contact is configured to receive a voltage to bias the first protection diode circuit in order to alter a point at which a PN junction of the first protection diode circuit becomes forward biased to avoid discharging charges associated with the target ion or molecule through the first protection diode circuit.

15. The method of fabricating an ISFET structure of claim 14 , further comprising:

forming a second protection diode circuit, wherein the second protection diode circuit includes at least one second PN junction between a second set of adjacent regions of opposite conductivity type formed within the substrate; and

electrically connecting the second protection diode circuit to the sense plate structure.

16. The method of fabricating an ISFET structure of claim 14 , wherein:

forming the first protection diode circuit further comprises forming a third region of the first conductivity type within the second well region; and

electrically coupling the contact to the first protection diode circuit comprises:

electrically coupling the contact to the third region.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2015
From: HOQUE, MD M.; PARRIS, PATRICE; CHEN, WEIZE; DE SOUZA, RICHARD
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