IP Library Patent Application 14141465
Patent Application
App. No. 14/141,465

EMICONDUCTOR DEVICE WITH DIE TOP POWER CONNECTIONS

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Quick Facts
Patent No.
US None
App. No.
14/141,465
Abstract

In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads. Bond wires electrically connect the power connection pads of the substrate to the power bond pads of the die, and exterior conductive structures electrically connect the power bond pads of the die to the distributed power feed pads of the die. The exterior conductive structures are printed or pasted onto the exterior die surface. Using exterior conductive structures instead of interior conductive traces (in the die) reduces resistive power losses and frees up more room for routing signals within the interior die layers.

Claims (28)

1 . A semiconductor device, comprising:

a substrate having power connection pads;

a die mounted on the substrate and having power bond pads and distributed power feed pads on an exterior surface of the die;

a first bond wire electrically connecting a first power connection pad of the substrate to a first power bond pad of the die; and

a first exterior conductive structure electrically connecting the first power bond pad of the die to a first distributed power feed pad of the die, wherein the first exterior conductive structure is not a bond wire.

2 . The semiconductor device of claim 1 , wherein:

the first power bond pad of the die is located at the periphery of the exterior surface of the die; and

the first distributed power feed pad of the die is located away from the periphery of the exterior surface of the die.

3 . The semiconductor device of claim 1 , wherein the first exterior conductive structure comprises a conductive element printed onto the exterior surface of the die.

4 . The semiconductor device of claim 3 , wherein the conductive element is printed onto the exterior surface of the die using stencil printing.

5 . The semiconductor device of claim 3 , wherein the conductive element is printed onto the exterior surface of the die using pen writing.

6 . The semiconductor device of claim 1 , wherein the first exterior conductive structure comprises a conductive element that is pasted onto the exterior surface of the die.

7 . The semiconductor device of claim 1 , further comprising:

one or more other bond wires connecting one or more other power connection pads of the substrate to one or more other power bond pads of the die; and

one or more other exterior conductive structures connecting the one or more other power bond pads of the die to one or more other distributed power feed pads of the die.

8 . The semiconductor device of claim 7 , wherein the one or more other exterior conductive structures each is printed onto the exterior surface of the die.

9 . The device of claim 7 , wherein the one or more other exterior conductive structures each are pasted onto the exterior surface of the die.

10 . A method of assembling a semiconductor device, the method comprising:

(a) mounting a semiconductor die on a substrate, wherein the substrate has power connection pads and the die has power bond pads and distributed power feed pads on an exterior surface of the die;

(b) forming exterior conductive structures on the exterior surface of the die, wherein the exterior conductive structures comprise a first exterior conductive structure electrically connecting a first power bond pad of the die to a first distributed power feed pad of the die, wherein the first exterior conductive structure is not a bond wire; and

(c) wire bonding a first bond wire between (i) a first power connection pad of the substrate and (ii) the first power bond pad of the die to form an electrical connection from the first power connection pad of the substrate and the first distributed power feed pad of the die.

11 . The method of claim 10 , wherein step (b) comprises:

(b1) applying a stencil to the exterior surface of the die, the stencil having openings corresponding to the exterior conductive structures of the semiconductor device;

(b2) applying a conductive material onto the stencil and into the openings of the stencil; and

(b3) removing the stencil and curing the conductive material to form the exterior conductive structures on the exterior surface of the die.

12 . The method of claim 10 , wherein the exterior conductive structures are formed using pen writing.

13 . The method of claim 10 , wherein the exterior conductive structures are formed using a printing technique.

14 . A packaged semiconductor device formed using the method of claim 10 .

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037926/0642 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037792/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037879/0581 →
CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0454 →
CORRECTIVE ASSIGNMENT OF INCORRECT NUMBER 14085520 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTON OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0568 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0390 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0420 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0399 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0790 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., COLLATERAL AGENT
Reel/Frame 032445/0689 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0577 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2013
From: MUNIANDY, KESVAKUMAR V.C.; KALANDAR, NAVAS KHAN ORATTI; TAN, LAN CHU
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031851/0440 →