IP Library Granted Patent US 9,099,487
Granted Patent B2
US 9,099,487 · App. 14/098,194 · Granted Aug 4, 2015

Zener diode devices and related fabrication methods

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,099,487
App. No.
14/098,194
Granted
Aug 4, 2015
Kind
B2
Abstract

Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

Claims (56)

1. A semiconductor device comprising:

a semiconductor substrate;

a first Zener diode structure on the semiconductor substrate, the first Zener diode structure including:

a first region having a first conductivity type and a first dopant concentration;

a second region having a second conductivity type and a second dopant concentration, the second region being adjacent to the first region to provide a vertical junction between the first region and the second region, the first region overlying the second region; and

a third region adjacent to the first region and the second region to provide a lateral junction between the third region and one of the first region or the second region, wherein the lateral junction is configured to influence a first reverse breakdown voltage of the vertical junction; and

a second Zener diode structure on the semiconductor substrate, the second Zener diode structure including:

a fourth region having the first conductivity type and the first dopant concentration;

a fifth region having the second conductivity type and the second dopant concentration, the fifth region being adjacent to the fourth region to provide a third junction between the fourth region and the fifth region; and

a sixth region adjacent to the fourth region and the fifth region to provide a fourth junction between the sixth region and one of the fourth region or the fifth region, wherein the fourth junction is configured to influence a second reverse breakdown voltage of the third junction, wherein:

the second reverse breakdown voltage and the first reverse breakdown voltage are different; and

a third reverse breakdown voltage of the lateral junction is greater than the first reverse breakdown voltage of the vertical junction.

2. The semiconductor device of claim 1 , wherein the lateral junction is angled with respect to the vertical junction.

3. The semiconductor device of claim 2 , wherein the lateral junction is substantially orthogonal to the vertical junction.

4. The semiconductor device of claim 1 , wherein the third region has the second conductivity type to provide the lateral junction between the third region and the first region.

5. The semiconductor device of claim 4 , wherein a dopant concentration of the third region is less than the second dopant concentration of the second region.

6. The semiconductor device of claim 4 , wherein the second dopant concentration of the second region is greater than the first dopant concentration of the first region.

7. The semiconductor device of claim 1 , wherein the third region has the first conductivity type to provide the lateral junction between the third region and the second region.

8. The semiconductor device of claim 7 , wherein the first dopant concentration of the first region is greater than the second dopant concentration of the second region.

9. The semiconductor device of claim 7 , wherein a dopant concentration of the third region is greater than the first dopant concentration of the first region.

10. The semiconductor device of claim 7 , wherein:

the first region comprises an anode region;

the second region comprises a cathode region; and

the third region comprises an anode enhancement region.

11. The semiconductor device of claim 1 , wherein the third region laterally circumscribes the first region and the second region.

12. The semiconductor device of claim 1 , wherein the third region and the sixth region have a third dopant concentration.

13. The semiconductor device of claim 1 , wherein a lateral dimension of one of the first region and the second region is different from that lateral dimension of one of the third region and the fourth region.

14. A method of fabricating a semiconductor device structure on a semiconductor substrate, the method comprising:

concurrently forming a first region and a second region in the semiconductor substrate, the first region and the second region having a first conductivity type and a first dopant concentration, the first region having a lateral dimension that is different from that lateral dimension of the second region; and

concurrently forming a third region and a fourth region in the semiconductor substrate, the third region and the fourth region having a second conductivity type and a second dopant concentration, the third region being adjacent to the first region to provide a first junction between the first region and the third region and the fourth region being adjacent to the second region to provide a second junction between the second region and the fourth region, wherein:

a first reverse breakdown voltage of the first junction is different from a second reverse breakdown voltage of the second junction;

a fifth region in the semiconductor substrate adjacent to the first region and the third region provides a third junction between the fifth region and one of the first region or the third region; and

the third junction influences the first reverse breakdown voltage of the first junction.

15. A semiconductor device comprising:

a semiconductor substrate;

a first Zener diode structure on the semiconductor substrate, the first Zener diode structure including:

an anode region having a first conductivity type and a first dopant concentration;

a cathode region having a second conductivity type and a second dopant concentration, the anode region overlying the cathode region and the cathode region being adjacent to the anode region to provide a vertical junction between the anode region and the cathode region; and

an anode enhancement region having the first conductivity type adjacent to the anode region and the cathode region to provide a lateral junction between the anode enhancement region and the cathode region, wherein the lateral junction is configured to influence a first reverse breakdown voltage of the vertical junction; and

a second Zener diode structure on the semiconductor substrate, the second Zener diode structure including:

a fourth region having the first conductivity type and the first dopant concentration;

a fifth region having the second conductivity type and the second dopant concentration, the fifth region being adjacent to the fourth region to provide a third junction between the fourth region and the fifth region; and

a sixth region adjacent to the fourth region and the fifth region to provide a fourth junction between the sixth region and one of the fourth region or the fifth region, wherein the fourth junction is configured to influence a second reverse breakdown voltage of the third junction, wherein:

the second reverse breakdown voltage and the first reverse breakdown voltage are different.

16. A semiconductor device comprising:

a semiconductor substrate;

a first Zener diode structure on the semiconductor substrate, the first Zener diode structure including:

a first region having a first conductivity type and a first dopant concentration;

a second region having a second conductivity type and a second dopant concentration, the second region being adjacent to the first region to provide a lateral junction between the first region and the second region; and

a third region adjacent to the first region and the second region to provide a vertical junction between the third region and one of the first region or the second region, wherein the vertical junction is configured to influence a first reverse breakdown voltage of the lateral junction; and

a second Zener diode structure on the semiconductor substrate, the second Zener diode structure including:

a fourth region having the first conductivity type and the first dopant concentration;

a fifth region having the second conductivity type and the second dopant concentration, the fifth region being adjacent to the fourth region to provide a third junction between the fourth region and the fifth region; and

a sixth region adjacent to the fourth region and the fifth region to provide a fourth junction between the sixth region and one of the fourth region or the fifth region, wherein the fourth junction is configured to influence a second reverse breakdown voltage of the third junction, wherein:

the second reverse breakdown voltage and the first reverse breakdown voltage are different; and

a third reverse breakdown voltage of the vertical junction is greater than the first reverse breakdown voltage of the lateral junction.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037926/0642 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037879/0581 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037792/0227 →
CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0454 →
CORRECTIVE ASSIGNMENT OF INCORRECT NUMBER 14085520 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTON OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0568 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0390 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0399 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0420 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0790 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., COLLATERAL AGENT
Reel/Frame 032445/0689 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0577 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2013
From: CHEN, WEIZE; LIN, XIN; PARRIS, PATRICE M.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 031725/0989 →