System in a package (SiP)
View Patent ↗A system in a package (SiP) includes a first semiconductor die having a nonvolatile memory and trim/repair circuitry, and a second semiconductor die having a volatile memory and trim/repair circuitry. The first and the second semiconductor die are in a same package. The nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die. The trim/repair circuitries of the first and second semiconductor die are configured to, in response to a reset of the second semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the second semiconductor die.
1. A system in a package (SiP), comprising:
a first semiconductor die having a nonvolatile memory and trim/repair circuitry; and
a second semiconductor die having a volatile memory and trim/repair circuitry, wherein the first and the second semiconductor die are in a same package, wherein the nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die, and wherein, trim/repair circuitries of the first and second semiconductor die are configured to, in response to a reset of the second semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the second semiconductor die.
2. The SiP of claim 1 , wherein the trim/repair circuitry of the second semiconductor die is configured to, in response to the reset of the second semiconductor die, send a request to the trim/repair circuitry of the first semiconductor die, and wherein the trim/repair circuitry of the first semiconductor die, in response to the request, provides the trim/repair values from the nonvolatile memory of the first semiconductor die to the trim/repair circuitry of the second semiconductor die.
3. The SiP of claim 2 , wherein the request includes a semiconductor die identifier.
4. The SiP of claim 3 , wherein the semiconductor die identifier identifies the second semiconductor die.
5. The SiP of claim 3 , further comprising a third semiconductor die, and wherein the semiconductor identifier identifies the third semiconductor die.
6. The SiP of claim 1 , further comprising:
a third semiconductor die having a volatile memory and trim/repair circuitry, wherein the first, second, and third semiconductor die are in the same package, and wherein trim/repair circuitries of the first and third semiconductor die are configured to, in response to a reset of the third semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the third semiconductor die.
7. The SiP of claim 1 , further comprising:
a third semiconductor die having a volatile memory and trim/repair circuitry, wherein the first, second, and third semiconductor die are in the same package, wherein trim/repair circuitries of the first, second, and third semiconductor die are configured to, in response to a reset of the third semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the third semiconductor die, in which the trim/repair values are provided by the trim/repair circuitry of the first semiconductor die to the trim/repair circuitry of the second semiconductor die, and subsequently, the trim/repair values are provided by the second semiconductor die to the trim/repair circuitry of the third semiconductor die.
8. The SiP of claim 7 , wherein the second semiconductor die comprises a system on a chip.
9. The SiP of claim 8 , wherein the first semiconductor die comprises a flash memory.
10. The SiP of claim 9 , wherein the third semiconductor die is characterized as an analog die.
11. A method comprising:
in a system in a package (SiP) having a first semiconductor die and a second semiconductor die packaged in a same package, receiving a reset;
in response to the reset, accessing trim/repair values stored in a nonvolatile memory of the first semiconductor die, wherein the trim/repair values include values corresponding to each of the first and second semiconductor die;
the first semiconductor die providing the accessed trim/repair values corresponding to the second semiconductor die to the second semiconductor die; and
the second semiconductor die receiving the trim/repair values corresponding to the second semiconductor die from the first semiconductor die and storing the received trim/repair values in a volatile memory of the second semiconductor die.
12. The method of claim 11 , further comprising:
determining the trim/repair values for each of the first and the second semiconductor die; and
after the determining and prior to the receiving the reset, storing the determined trim/repair values into the nonvolatile memory of the first semiconductor die.
13. The method of claim 11 , wherein, during normal operation of the second semiconductor die, using the trim/repair values corresponding to the second semiconductor die stored in the volatile memory.
14. The method of claim 11 , further comprising:
in response to the reset, the second semiconductor die sending a request to the first semiconductor die for the time/repair values corresponding to the second semiconductor die.
15. The method of claim 14 , wherein the request comprises a die identifier which identifies one of a group consisting of the second semiconductor die and a number of bytes requested.
16. The method of claim 11 , wherein the SiP further comprises a third semiconductor die in the same package and wherein the trim/repair values in the nonvolatile memory of the first semiconductor die includes values corresponding to the third semiconductor die, the method further comprising:
in response to the reset, the third semiconductor die providing a request to the second semiconductor die;
the second semiconductor die providing the request to the first semiconductor die;
the first semiconductor die, in response to the request, providing the trim/repair values corresponding to the third semiconductor die to the second semiconductor die;
the second semiconductor die providing the trim/repair values corresponding to the third semiconductor die to the third semiconductor die; and
storing the trim/repair values corresponding to the third semiconductor die in volatile memory of the third semiconductor die.
17. The method of claim 16 , wherein the request comprises a die identifier which identifies the third semiconductor die.
18. A system in a package (SiP), comprising:
a first semiconductor die having a nonvolatile memory and trim/repair circuitry; and
a second semiconductor die having a volatile memory and trim/repair circuitry, wherein the first and the second semiconductor die are in a same package, wherein the nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die, and wherein, the trim/repair circuitry of the second semiconductor die is configured to, in response to a reset of the second semiconductor die, provide a request to the first semiconductor die to obtain the trim/repair values for the second semiconductor die, and wherein the trim/repair circuitry of the first semiconductor die is configured to, in response to the request, access the nonvolatile memory to obtain the trim/repair values for the second semiconductor die from the nonvolatile memory and provide trim/repair values for the second semiconductor die to the second semiconductor die for storage into the volatile memory.
19. The system of claim 18 , further comprising:
a third semiconductor die having a volatile memory and trim/repair circuitry, wherein the first, second, and third semiconductor die is in the same package, wherein the nonvolatile memory of the first semiconductor die is further configured to store trim/repair values for the third semiconductor die, and wherein the trim/repair circuitry of the third semiconductor die is configured to, in response to a reset of the third semiconductor die, provide a second request to the first semiconductor die to obtain the trim/repair values for the third semiconductor die, and wherein the trim/repair circuitry of the first semiconductor die is configured to, in response to the second request, access the nonvolatile memory to obtain the trim/repair values for the third semiconductor die from the nonvolatile memory and provide trim/repair values for the third semiconductor die for storage into the volatile memory of the third semiconductor die.
20. The system of claim 19 , wherein the trim/repair circuitry of the first semiconductor die is configured to provide the obtained trim/repair values for the third semiconductor die to the second semiconductor die, and the trim/repair circuitry of the second semiconductor die is configured to provide the trim/repair values for the third semiconductor die to the third semiconductor die for storage into the volatile memory of the third semiconductor die.